SLUSF12A april 2023 – august 2023 UCC14131-Q1
PRODUCTION DATA
The UCC14131-Q1 module is designed to allow a microcontroller host to enable it with the ENA pin for proper system sequencing. The PG output also allows the host to monitor the status of the module. The PG pin goes low when there are no faults and the output voltage is within ±10% of the set target output voltage. The output voltage is meant to power a gate driver for IGBT, SiC FET, or GaN power devices. The host can start sending PWM control to the gate driver after the PG pin goes low to ensure proper sequencing. Shown below is the system diagram for the dual-output with postive and negative configuration and a system diagram for the dual-output with two postive configuration.