SLUSDG3D
August 2018 – April 2021
UCC21530-Q1
PRODUCTION DATA
1
Features
2
Applications
3
Description
4
Revision History
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Power Ratings
6.6
Insulation Specifications
6.7
Safety-Related Certifications
6.8
Safety-Limiting Values
6.9
Electrical Characteristics
6.10
Switching Characteristics
6.11
Insulation Characteristics Curves
6.12
Typical Characteristics
7
Parameter Measurement Information
7.1
Propagation Delay and Pulse Width Distortion
7.2
Rising and Falling Time
7.3
Input and Enable Response Time
7.4
Programable Dead Time
7.5
Power-Up UVLO Delay to OUTPUT
7.6
CMTI Testing
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
VDD, VCCI, and Under Voltage Lock Out (UVLO)
8.3.2
Input and Output Logic Table
8.3.3
Input Stage
8.3.4
Output Stage
8.3.5
Diode Structure in UCC21530-Q1
8.4
Device Functional Modes
8.4.1
Enable Pin
8.4.2
Programmable Dead Time (DT) Pin
8.4.2.1
DT Pin Tied to VCC
8.4.2.2
DT Pin Connected to a Programming Resistor between DT and GND Pins
9
Layout
9.1
Layout Guidelines
9.1.1
Component Placement Considerations
9.1.2
Grounding Considerations
9.1.3
High-Voltage Considerations
9.1.4
Thermal Considerations
9.2
Layout Example
10
Device and Documentation Support
10.1
Documentation Support
10.1.1
Related Documentation
10.2
Receiving Notification of Documentation Updates
10.3
Community Resources
10.4
Trademarks
Package Options
Mechanical Data (Package|Pins)
DWK|14
MPCS001
|
Thermal pad, mechanical data (Package|Pins)
Orderable Information
slusdg3d_oa
1
Features
AEC-Q100 qualified with:
Device temperature grade 1
Device HBM ESD classification level H2
Device CDM ESD classification level C6
Functional Safety Quality-Managed
Documentation available to aid functional safety system design
Universal: dual low-side, dual high-side or half-bridge driver
Wide body SOIC-14 (DWK) package
3.3-mm spacing between driver channels
Switching parameters:
19-ns typical propagation delay
10-ns minimum pulse width
5-ns maximum delay matching
6-ns maximum pulse-width distortion
Common-mode transient immunity (CMTI) greater than 100-V/ns
Isolation barrier life >40 years
4-A peak source, 6-A peak sink output
TTL and CMOS compatible inputs
3-V to 18-V input VCCI range
Up to 25-V VDD output drive supply
8-V and 12-V VDD UVLO options
Programmable overlap and dead time
Rejects input pulses and noise transients shorter than 5 ns
Operating temperature range –40 to +125°C
Safety-related certifications:
8000-V
PK
isolation per DIN V VDE V 0884-11 :2017-01
5.7-kV
RMS
isolation for 1 minute per UL 1577
CSA certification per IEC 60950-1, IEC 62368-1, IEC 61010-1 and IEC 60601-1 end equipment standards
CQC certification per GB4943.1-2011