Automotive, 4-A, 6-A, 5.7-kVrms isolated dual-channel gate driver with enable
Product details
Parameters
Package | Pins | Size
Features
- Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
- Wide Body SOIC-14 (DWK) Package
- 3.3mm spacing between driver channels
- Switching Parameters:
- 19-ns Typical Propagation Delay
- 10-ns Minimum Pulse Width
- 5-ns Maximum Delay Matching
- 6-ns Maximum Pulse-Width Distortion
- Common-Mode Transient Immunity (CMTI) Greater than 100-V/ns
- Surge Immunity up to 12.8-kVPK
- Isolation Barrier Life >40 Years
- 4-A Peak Source, 6-A Peak Sink Output
- TTL and CMOS Compatible Inputs
- 3-V to 18-V Input VCCI Range
- Up to 25-V VDD Output Drive Supply
- Programmable Overlap and Dead Time
- Rejects Input Pulses and Noise Transients Shorter than 5 ns
- Operating Temperature Range –40 to +125°C
- Safety-Related Certifications:
- 8000-VPK Isolation per DIN V VDE V 0884-11 :2017-01 (Planned)
- 5.7-kVRMS Isolation for 1 Minute per UL 1577
- CSA Certification per IEC 60950-1, IEC 62368-1, IEC 61010-1 and IEC 60601-1 End Equipment Standards (Planned)
- CQC Certification per GB4943.1-2011 (Planned)
- AEC-Q100 Qualified With:
- Device Temperature Grade 1
- Device HBM ESD Classification Level H2
- Device CDM ESD Classification Level C6
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Description
The UCC21530-Q1 is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current. It is designed to drive IGBTs and SiC MOSFETs up to 5-MHz with best-in-class propagation delay and pulse-width distortion.
The input side is isolated from the two output drivers by a 5.7-kVRMS reinforced isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two secondary-side drivers allows a working voltage of up to 1850 V.
This driver can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver with programmable dead time (DT). The EN pin pulled low shuts down both outputs simultaneously and allows for normal operation when left open or pulled high. As a fail-safe measure, primary-side logic failures force both outputs low.
The device accepts VDD supply voltages up to 25 V. A wide input VCCI range from 3 V to 18 V makes the driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under voltage lock-out (UVLO) protection.
With all these advanced features, the UCC21530-Q1 enables high efficiency, high power density, and robustness in a wide variety of power applications.

Request more information
The UCC21530-Q1 safety manual and safety fit rate report are available. Request now
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | UCC21530-Q1 4-A, 6-A, 5.7-kVRMS Isolated Dual-Channel Gate Driver with 3.3-mm Channel-to-Channel Spacing datasheet (Rev. C) | Mar. 08, 2019 |
More literature | VDE certificate for reinforced isolation for DIN VDE V 0884-11:2017-01 (Rev. N) | Nov. 13, 2019 | |
More literature | CSA Product Certificate (Rev. A) | Aug. 15, 2019 | |
More literature | UL Certification E181974 Vol 4. Sec 7 (Rev. B) | Jul. 22, 2019 | |
Technical article | Searching for the newest innovations in power? Find them at APEC | Feb. 09, 2019 | |
Technical article | How to achieve higher system robustness in DC drives, part 3: minimum input pulse | Sep. 19, 2018 | |
Technical article | How to achieve higher system robustness in DC drives, part 2: interlock and deadtime | May 30, 2018 | |
Technical article | Boosting efficiency for your solar inverter designs | May 24, 2018 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
Features
- Universal: Dual Low-Side, Dual High-Side or Half-Bridge Driver
- Common-Mode Transient Immunity CMTI Greater than 100 V/ns
- Programmable Overlap and Dead Time
- 5.7-kVrms reinforced isolation
- Wide Body SOIC-14 (DWK) Package with 3.3 mm spacing between channels on secondary side
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download TIDM-02009 BOM.pdf (450KB) -
download TIDM-02009 Assembly Files.zip (2185KB) -
download TIDM-02009 Layer Plots.zip (12350KB) -
download TIDM-02009 CAD Files.zip (93383KB) -
download TIDM-02009 Gerber.zip (12316KB)
Design files
-
download PMP21553 Assembly Drawing.pdf (110KB) -
download PMP21553 PCB.pdf (475KB) -
download PMP21553 Gerber.zip (1804KB) -
download PMP21561 Assembly Drawing.pdf (110KB) -
download PMP21561 PCB.pdf (472KB) -
download PMP21561 Gerber.zip (1795KB) -
download PMP21553 BOM (Rev. A).pdf (94KB) -
download PMP21561 BOM (Rev. A).pdf (94KB) -
download PMP21561 CAD Files (Rev. A).zip (592KB) -
download PMP21495 BOM.pdf (109KB) -
download PMP21495 Assembly Drawing.pdf (898KB) -
download PMP21495 PCB.pdf (2843KB) -
download PMP21495 CAD Files.zip (3137KB) -
download PMP21495 Gerber.zip (3381KB) -
download PMP21553 CAD Files (Rev. B).zip (592KB)
Design files
-
download TIDA-01605 Altium (Rev. A).zip (789KB) -
download TIDA-01605 BOM (Rev. A).pdf (55KB) -
download TIDA-01605 Gerber (Rev. A).zip (295KB) -
download TIDA-01605 Assembly Drawing (Rev. A).pdf (1731KB) -
download TIDA-01605 PCB (Rev. A).pdf (6671KB)
Design files
-
download PMP21999 BOM Files.zip (396KB) -
download PMP21999 Assembly Files.zip (1473KB) -
download PMP21999 Layer Plots.zip (2169KB) -
download PMP21999 CAD Files.zip (8523KB) -
download PMP21999 Gerber.zip (8676KB)
Design files
-
download PMP21561 Assembly Drawing.pdf (110KB) -
download PMP21561 PCB.pdf (472KB) -
download PMP21561 Gerber.zip (1795KB) -
download PMP21561 BOM (Rev. A).pdf (94KB) -
download PMP21561 CAD Files (Rev. A).zip (592KB)
Design files
-
download PMP21553 Assembly Drawing.pdf (110KB) -
download PMP21553 PCB.pdf (475KB) -
download PMP21553 Gerber.zip (1804KB) -
download PMP21553 BOM (Rev. A).pdf (94KB) -
download PMP21553 CAD Files (Rev. B).zip (592KB)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (DWK) | 14 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
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