Product details

Number of channels (#) 2 Isolation rating (Vrms) 5700 Power switch IGBT, SiCFET Peak output current (A) 6 DIN V VDE V 0884-10 transient overvoltage rating (Vpk) 8000 DIN V VDE V 0884-10 working voltage (Vpk) 2121 Output VCC/VDD (Max) (V) 25 Output VCC/VDD (Min) (V) 14.7 Input VCC (Min) (V) 3 Input VCC (Max) (V) 18 Prop delay (ns) 19 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 12
Number of channels (#) 2 Isolation rating (Vrms) 5700 Power switch IGBT, SiCFET Peak output current (A) 6 DIN V VDE V 0884-10 transient overvoltage rating (Vpk) 8000 DIN V VDE V 0884-10 working voltage (Vpk) 2121 Output VCC/VDD (Max) (V) 25 Output VCC/VDD (Min) (V) 14.7 Input VCC (Min) (V) 3 Input VCC (Max) (V) 18 Prop delay (ns) 19 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 12
SOIC (DWK) 14 77 mm² 10.3 x 7.5
  • AEC-Q100 qualified with:
    • Device temperature grade 1
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C6
  • Functional Safety Quality-Managed
  • Universal: dual low-side, dual high-side or half-bridge driver
  • Wide body SOIC-14 (DWK) package
  • 3.3-mm spacing between driver channels
  • Switching parameters:
    • 19-ns typical propagation delay
    • 10-ns minimum pulse width
    • 5-ns maximum delay matching
    • 6-ns maximum pulse-width distortion
  • Common-mode transient immunity (CMTI) greater than 100-V/ns
  • Isolation barrier life >40 years
  • 4-A peak source, 6-A peak sink output
  • TTL and CMOS compatible inputs
  • 3-V to 18-V input VCCI range
  • Up to 25-V VDD output drive supply
    • 8-V and 12-V VDD UVLO options
  • Programmable overlap and dead time
  • Rejects input pulses and noise transients shorter than 5 ns
  • Operating temperature range –40 to +125°C
  • Safety-related certifications:
    • 8000-VPK isolation per DIN V VDE V 0884-11 :2017-01
    • 5.7-kVRMS isolation for 1 minute per UL 1577
    • CSA certification per IEC 60950-1, IEC 62368-1, IEC 61010-1 and IEC 60601-1 end equipment standards
    • CQC certification per GB4943.1-2011
  • AEC-Q100 qualified with:
    • Device temperature grade 1
    • Device HBM ESD classification level H2
    • Device CDM ESD classification level C6
  • Functional Safety Quality-Managed
  • Universal: dual low-side, dual high-side or half-bridge driver
  • Wide body SOIC-14 (DWK) package
  • 3.3-mm spacing between driver channels
  • Switching parameters:
    • 19-ns typical propagation delay
    • 10-ns minimum pulse width
    • 5-ns maximum delay matching
    • 6-ns maximum pulse-width distortion
  • Common-mode transient immunity (CMTI) greater than 100-V/ns
  • Isolation barrier life >40 years
  • 4-A peak source, 6-A peak sink output
  • TTL and CMOS compatible inputs
  • 3-V to 18-V input VCCI range
  • Up to 25-V VDD output drive supply
    • 8-V and 12-V VDD UVLO options
  • Programmable overlap and dead time
  • Rejects input pulses and noise transients shorter than 5 ns
  • Operating temperature range –40 to +125°C
  • Safety-related certifications:
    • 8000-VPK isolation per DIN V VDE V 0884-11 :2017-01
    • 5.7-kVRMS isolation for 1 minute per UL 1577
    • CSA certification per IEC 60950-1, IEC 62368-1, IEC 61010-1 and IEC 60601-1 end equipment standards
    • CQC certification per GB4943.1-2011

The UCC21530-Q1 is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current. It is designed to drive IGBTs, Si MOSFETs, and SiC MOSFETs up to 5-MHz with best-in-class propagation delay and pulse-width distortion.

The input side is isolated from the two output drivers by a 5.7-kVRMS reinforced isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two secondary-side drivers allows a working voltage of up to 1850 V.

This driver can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver with programmable dead time (DT). The EN pin pulled low shuts down both outputs simultaneously and allows for normal operation when left open or pulled high. As a fail-safe measure, primary-side logic failures force both outputs low.

The device accepts VDD supply voltages up to 25 V. A wide input VCCI range from 3 V to 18 V makes the driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under voltage lock-out (UVLO) protection.

The UCC21530-Q1 is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current. It is designed to drive IGBTs, Si MOSFETs, and SiC MOSFETs up to 5-MHz with best-in-class propagation delay and pulse-width distortion.

The input side is isolated from the two output drivers by a 5.7-kVRMS reinforced isolation barrier, with a minimum of 100-V/ns common-mode transient immunity (CMTI). Internal functional isolation between the two secondary-side drivers allows a working voltage of up to 1850 V.

This driver can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver with programmable dead time (DT). The EN pin pulled low shuts down both outputs simultaneously and allows for normal operation when left open or pulled high. As a fail-safe measure, primary-side logic failures force both outputs low.

The device accepts VDD supply voltages up to 25 V. A wide input VCCI range from 3 V to 18 V makes the driver suitable for interfacing with both analog and digital controllers. All the supply voltage pins have under voltage lock-out (UVLO) protection.

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Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

UCC21530EVM-286 — UCC21530 isolated dual-channel driver evaluation module

UCC21530EVM-286 is designed for evaluating UCC21530DWK, which is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current, 12V UVLO, Enable (Active High) Function and 3.3 mm creepage between channels . This EVM could be served as a reference design for driving IGBTS and SiC (...)
Not available on TI.com
Simulation model

UCC21530 PSpice Transient Model

SLUM655.ZIP (23 KB) - PSpice Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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User guide: PDF
Schematic: PDF
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TIDM-02009 — ASIL D safety concept-assessed high-speed traction, bi-directional DC/DC conversion reference design

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Schematic: PDF
Reference designs

TIDA-01605 — Automotive Dual Channel SiC MOSFET Gate Driver Reference Design with Two Level Turn-off Protection

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Schematic: PDF
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Schematic: PDF
Reference designs

PMP21561 — Safety isolated secondary SiC MOSFET driver reference design

This reference design provides an integrated high and low side isolated secondary gate driver solution for an automotive battery charging system incorporating two push-pull SN6505B transformer drivers and the isolated dual-channel gate driver UCC21521C.
Schematic: PDF
Reference designs

PMP21553 — Safety isolated primary SiC MOSFET driver reference design

This reference design provides an integrated high and low side isolated primary gate driver solution for an automotive battery charging system incorporating two push-pull SN6505B transformer drivers and the isolated dual-channel gate driver UCC21521C.
Schematic: PDF
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