SLUSDG3D August   2018  – April 2021 UCC21530-Q1

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 Input and Enable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 Power-Up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC21530-Q1
    4. 8.4 Device Functional Modes
      1. 8.4.1 Enable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 DT Pin Tied to VCC
        2. 8.4.2.2 DT Pin Connected to a Programming Resistor between DT and GND Pins
  9. 9 Layout
    1. 9.1 Layout Guidelines
      1. 9.1.1 Component Placement Considerations
      2. 9.1.2 Grounding Considerations
      3. 9.1.3 High-Voltage Considerations
      4. 9.1.4 Thermal Considerations
    2. 9.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2 Layout Example

Figure 9-1shows a 2-layer PCB layout example with the signals and key components labeled.

GUID-504369A2-03C3-4DE1-B6A0-A33C01D3B298-low.pngFigure 9-1 Layout Example

Figure 9-2 and Figure 9-3 shows top and bottom layer traces and copper.

Note:

There are no PCB traces or copper between the primary and secondary side, which ensures isolation performance.

PCB traces between the high-side and low-side gate drivers in the output stage are increased to maximize the creepage distance for high-voltage operation, which will also minimize cross-talk between the switching node VSSA (SW), where high dv/dt may exist, and the low-side gate drive due to the parasitic capacitance coupling.

GUID-63A0822E-C4D2-4046-80EA-DA2FD13627F7-low.pngFigure 9-2 Top Layer Traces and Copper
GUID-3B6C6AEF-B2D0-44A6-8162-24F18A04A85F-low.pngFigure 9-3 Bottom Layer Traces and Copper

Figure 9-4 and Figure 9-5 are 3D layout pictures with top view and bottom views.

Note:

The location of the PCB cutout between the primary side and secondary sides, which ensures isolation performance.

GUID-AB3918B0-2238-4C35-8CE5-5A5421D3C12B-low.pngFigure 9-4 3-D PCB Top View
GUID-C3FF683F-EF4E-4331-B62E-1960630ABAA0-low.pngFigure 9-5 3-D PCB Bottom View