SLUSAF9B February   2011  – July 2015 UCC27200A , UCC27201A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Stages
        1. 7.3.1.1 UVLO (Undervoltage Lockout)
        2. 7.3.1.2 Level Shift
        3. 7.3.1.3 Boot Diode
        4. 7.3.1.4 Output Stages
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Switching the MOSFETs
        2. 8.2.2.2 Dynamic Switching of the MOSFETs
        3. 8.2.2.3 Delay Matching and Narrow Pulse Widths
        4. 8.2.2.4 Boot Diode Performance
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Related Links
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

D Package
8-Pin SOIC
Top View
UCC27200A UCC27201A pin1.gif
DDA Package
8-Pin SOIC With Exposed PowerPAD
Top View
UCC27200A UCC27201A pin2.gif
DRM Package
8-Pin SON
Top View
UCC27200A UCC27201A pin3.gif
DRC Package
9-Pin SON
Top View
UCC27200A UCC27201A pin4_lusaf9.gif
DPR Package
10-Pin SON
Top View
UCC27200A UCC27201A SON_10_lusaf9.gif

Pin Functions

PIN I/O DESCRIPTION
NAME DRM/D/DDA DRC DPR
VDD 1 1 1 I Positive supply to the lower gate driver. De-couple this pin to VSS (GND). Typical decoupling capacitor range is 0.22 μF to 1.0 μF.
HB 2 2 2 I High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022 μF to 0.1 μF, the value is dependant on the gate charge of the high-side MOSFET however.
HO 3 3 3 O High-side output. Connect to the gate of the high-side power MOSFET.
HS 4 4 4 I High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin.
HI 5 6 7 I High-side input.
LI 6 7 8 I Low-side input.
VSS 7 8 9 O Negative supply terminal for the device which is generally grounded.
LO 8 9 10 O Low-side output. Connect to the gate of the low-side power MOSFET.
N/C — 5 5/6 — No connection. Pins labeled N/C have no connection.
PowerPAD(1) — — — — Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance.
(1) Pin VSS and the exposed thermal die pad are internally connected on the DDA and DRM packages only. Electrically referenced to VSS (GND).