UCC27200A
3-A, 120-V half bridge gate driver with 8-V UVLO, negative voltage handling and CMOS inputs
UCC27200A
- Drives Two N-Channel MOSFETs in High-Side
and Low-Side Configuration - Negative Voltage Handling on HS (–18V)
- Maximum Boot Voltage 120 V
- Maximum VDD Voltage 20 V
- On-Chip 0.65-V VF, 0.6-Ω RD Bootstrap Diode
- Greater than 1 MHz of Operation
- 20-ns Propagation Delay Times
- 3-A Sink, 3-A Source Output Currents
- 8-ns Rise/7-ns Fall Time with 1000-pF Load
- 1-ns Delay Matching
- Undervoltage Lockout for High-Side and Low-Side
Driver - Offered in 8-Pin SOIC (D), PowerPAD™ SOIC-8
(DDA), SON-8 (DRM), SON-9 (DRC) and SON-10
(DPR) Packages - Specified from –40°C to 140°C
The UCC2720xA family of high-frequency N-channel MOSFET drivers include a 120-V bootstrap diode and high-side/low-side driver with independent inputs for maximum control flexibility. This allows for N-channel MOSFET control in half-bridge, full-bridge, two-switch forward and active clamp forward converters. The low-side and the high-side gate drivers are independently controlled and matched to 1-ns between the turn-on and turn-off of each other. The UCC2720xA are based on the popular UCC27200/1 drivers, but offer some enhancements. In order to improve performance in noisy power supply environments the UCC2720xA has an enhanced ESD input structure and also has the ability to withstand a maximum of 18 V on its HS pin.
An on-chip bootstrap diode eliminates the external discrete diodes. Under-voltage lockout is provided for both the high-side and the low-side drivers forcing the outputs low if the drive voltage is below the specified threshold.
Two versions of the UCC27200A are offered. The UCC27200A has high-noise immune CMOS input thresholds while the UCC27201A has TTL-compatible thresholds.
Both devices are offered in an 8-pin SOIC (D), PowerPad SOIC-8 (DDA), SON-8 (DRM) package, a 9-pin SON-9 (DRC) package and a 10-pin SON-10 (DPR) package.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | UCC2720xA 120-V Boot, 3-A Peak, High-Frequency, High-Side and Low-Side Driver datasheet (Rev. B) | PDF | HTML | 31 Aug 2015 |
Application note | External Gate Resistor Selection Guide (Rev. A) | 28 Feb 2020 | ||
Application note | Understanding Peak IOH and IOL Currents (Rev. A) | 28 Feb 2020 | ||
More literature | Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) | 29 Oct 2018 | ||
Technical article | How to achieve higher system robustness in DC drives, part 3: minimum input pulse | 19 Sep 2018 | ||
Selection guide | Power Management Guide 2018 (Rev. R) | 25 Jun 2018 | ||
Technical article | How to achieve higher system robustness in DC drives, part 2: interlock and deadtime | 30 May 2018 | ||
Technical article | How to achieve higher system robustness in DC drives, part 1: negative voltage | 17 Apr 2018 | ||
Technical article | A bite-size gate drive: replacing BJTs with an integrated solution | 30 Nov 2017 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
UCC27200 and UCC27200A TINA-TI Transient Reference Design
UCC27200 and UCC27200A TINA-TI Transient Spice Model
UCC27200 and UCC27200A Unencrypted PSpice Transient Model
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
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Package | Pins | Download |
---|---|---|
HSOIC (DDA) | 8 | View options |
SOIC (D) | 8 | View options |
VSON (DRC) | 9 | View options |
VSON (DRM) | 8 | View options |
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