SLUSAT7F November   2011  – December 2014 UCC27210 , UCC27211

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Switching Characteristics: Propagation Delays
    7. 7.7  Switching Characteristics: Delay Matching
    8. 7.8  Switching Characteristics: Output Rise and Fall Time
    9. 7.9  Switching Characteristics: Miscellaneous
    10. 7.10 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Input Stages
      2. 8.3.2 Undervoltage Lockout (UVLO)
      3. 8.3.3 Level Shift
      4. 8.3.4 Boot Diode
      5. 8.3.5 Output Stages
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Threshold Type
        2. 9.2.2.2 VDD Bias Supply Voltage
        3. 9.2.2.3 Peak Source and Sink Currents
        4. 9.2.2.4 Propagation Delay
        5. 9.2.2.5 Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DRM|8
  • DPR|10
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

UCC27210 UCC27211 pins_lusat7.gif

Pin Functions

PIN I/O DESCRIPTION
NAME D/DDA/DRM DPR
VDD 1 1 P Positive supply to the lower-gate driver. Decouple this pin to VSS (GND). Typical decoupling capacitor range is 0.22 µF to 4.7 µF (See (2)).
HB 2 2 P High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022 µF to 0.1 µF. The capacitor value is dependant on the gate charge of the high-side MOSFET and should also be selected based on speed and ripple criteria
HO 3 3 O High-side output. Connect to the gate of the high-side power MOSFET.
HS 4 4 P High-side source connection. Connect to source of high-side power MOSFET. Connect the negative side of bootstrap capacitor to this pin.
HI 5 7 I High-side input.(3)
LI 6 8 I Low-side input.(3)
VSS 7 9 G Negative supply terminal for the device which is generally grounded.
LO 8 10 O Low-side output. Connect to the gate of the low-side power MOSFET.
N/C — 5/6 — Not connected.
PowerPAD™(1) Pad Pad G Used on the DDA, DRM and DPR packages only. Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance.
(1) The PowerPAD™ is not directly connected to any leads of the package. However it is electrically and thermally connected to the substrate which is the ground of the device.
(2) For cold temperature applications we recommend the upper capacitance range. Attention should also be made to PCB layout - see Layout.
(3) HI or LI input is assumed to connect to a low impedance source signal. The source output impedance is assumed less than 100 Ω. If the source impedance is greater than 100 Ω, add a bypassing capacitor, each, between HI and VSS and between LI and VSS. The added capacitor value depends on the noise levels presented on the pins, typically from 1 nF to 10 nF should be effective to eliminate the possible noise effect. When noise is present on two pins, HI or LI, the effect is to cause HO and LO malfunctions to have wrong logic outputs.