SLUSFV5 July   2025 UCC27302A

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages and Interlock
      2. 6.3.2 Enable
      3. 6.3.3 Undervoltage Lockout (UVLO)
      4. 6.3.4 Level Shifter
      5. 6.3.5 Boot Diode
      6. 6.3.6 Output Stages
      7. 6.3.7 Negative Voltage Transients
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Threshold Type
        2. 7.2.2.2 VDD Bias Supply Voltage
        3. 7.2.2.3 Peak Source and Sink Currents
        4. 7.2.2.4 Propagation Delay
        5. 7.2.2.5 Power Dissipation
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Considerations
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
    2. 8.2 Documentation Support
      1. 8.2.1 Related Documentation
    3. 8.3 Receiving Notification of Documentation Updates
    4. 8.4 Support Resources
    5. 8.5 Trademarks
    6. 8.6 Electrostatic Discharge Caution
    7. 8.7 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
  • DRC|10
  • DDA|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.6 Switching Characteristics

VDD = VHB = 12 V, VHS = VSS = 0 V, No load on LO or HO, TA = TJ = –40°C to +150°C (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
PROPAGATION DELAYS
tDLFFVLI falling to VLO fallingCLOAD = 0 pF, from VLIT of LI to 90% of LO falling101930ns
tDHFF VHI falling to VHO fallingCLOAD = 0 pF,  from VLIT of HI to 90% of HO falling101930ns
tDLRR VLI rising to VLO risingCLOAD = 0 pF, from VHIT of LI to 10% of LO rising102042ns
tDHRRVHI rising to VHO risingCLOAD = 0 pF, CLOAD = 0 pF, from VHIT of HI to 10% of HO rising102042ns
DELAY MATCHING
tMONLI ON, HI OFFTJ = 25°C, from 10% of LO rising to 90% of HO falling49.5ns
tMONLI ON, HI OFFTJ = -40°C to 150°C, from 10% of LO rising to 90% of HO falling417ns
tMOFFLI OFF, HI ONTJ = 25°C, from 90% of LO falling to 10% of HO rising49.5ns
tMOFFLI OFF, HI ONTJ = -40°C to 150°C, from 90% of LO falling to 10% of HO rising417ns
OUTPUT RISE AND FALL TIME
tR_LOLO rise timeCLOAD = 1000 pF, from 10% to 90%7.2ns
tR_HOHO rise timeCLOAD = 1000 pF, from 10% to 90%7.2ns
tF_LOLO fall timeCLOAD = 1000 pF, from 90% to 10%5.5ns
tF_HOHO fall timeCLOAD = 1000 pF, from 90% to 10%5.5ns
tR_LO_p1LO rise time (3 V to 9 V)CLOAD = 0.1 μF, (3V to 9V)0.270.6μs
tR_HO_p1HO rise time (3 V to 9 V)CLOAD = 0.1 μF, (3V to 9V)0.270.6μs
tF_LO_p1LO fall time (9 V to 3 V)CLOAD = 0.1 μF, (9V to 3V)0.160.4μs
tF_HO_p1HO fall time (9 V to 3 V)CLOAD = 0.1 μF, (9V to 3V)0.160.4μs
MISCELLANEOUS
tIN_PWMinimum input pulse width that changes the output  LO40ns
tIN_PWMinimum input pulse width that changes the output  HO40ns
tOFF_BSDBootstrap diode turnoff time(1)(2)IF = 20 mA, IREV = 0.5 A(3)20ns
(1) Parameter not tested in production.
(2) Typical values for TA = 25°C.
(3) IF: Forward current applied to bootstrap diode, IREV: Reverse current applied to bootstrap diode.