SLUS678D March   2008  – November 2023 UCC27324-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Overall Electrical Characteristics
    6. 5.6  Power Dissipation Characteristics
    7. 5.7  Input (INA, INB) Electrical Characteristics
    8. 5.8  Output (OUTA, OUTB) Electrical Characteristics
    9. 5.9  Switching Characteristics
    10. 5.10 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stage
      2. 6.3.2 Output Stage
    4. 6.4 Device Functional Modes
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Parallel Outputs
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Propagation Delay
        2. 7.2.2.2 Source and Sink Capabilities During Miller Plateau
        3. 7.2.2.3 Supply Voltage (VDD)
        4. 7.2.2.4 Drive Current and Power Requirements
      3. 7.2.3 Application Curve
  9. 8 Power Supply Recommendations
  10. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
    3. 9.3 Thermal Considerations
  11. 10Device and Documentation Support
    1. 10.1 Third-Party Products Disclaimer
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.3 Application Curve

Figure 7-5 shows the circuit performance achievable with a single driver (half of the 8-pin device) driving a 10-nF load. The input pulse width (not shown) is set to 300 ns to show both transitions in the output waveform. The rising and falling edges of the switching waveforms are fairly linear which is because of the constant output current characteristic of the driver as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.

Sink and source currents of the driver are dependent upon the VDD value and the output capacitive load. The larger the VDD value the higher the current capability, and the larger the capacitive load the higher the current sink/source capability. Trace resistance and inductance, including wires and cables for testing, slows down the rise and fall times of the outputs which reduces the current capabilities of the driver. To achieve higher current results, reduce resistance and inductance on the board as much as possible and increase the capacitive output load value to swap out the effect of the inductance values.

GUID-1C1161EA-7CDE-4F5E-9BE5-CF1AC7292F60-low.gif Figure 7-5 Single Driver With 10-nF Load, 300-ns Pulse-Width Input