Table 1. UCC2752x Family of Features and Benefits

8.3.1 V_DD and Undervoltage Lockout

The UCC2752x devices have internal undervoltage-lockout (UVLO) protection feature on the V_DD pin supply circuit blocks. When V_DD is rising and the level is still below UVLO threshold, this circuit holds the output LOW, regardless of the status of the inputs. The UVLO is typically 4.2 V with 300-mV typical hysteresis. This hysteresis prevents chatter when low V_DD supply voltages have noise from the power supply and also when there are droops in the V_DD bias voltage when the system commences switching and there is a sudden increase in I_DD. The capability to operate at low voltage levels such as below 5 V, along with best-in-class switching characteristics, is especially suited for driving emerging GaN power semiconductor devices.

For example, at power up, the UCC2752x driver-device output remains LOW until the V_DD voltage reaches the UVLO threshold if Enable pin is active or floating. The magnitude of the OUT signal rises with V_DD until steady-state V_DD is reached. The non-inverting operation in Figure 26 shows that the output remains LOW until the UVLO threshold is reached, and then the output is in-phase with the input. The inverting operation in Figure 27 shows that the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with the input. With UCC27526 the output turns to high-state only if INX+ is high and INX– is low after the UVLO threshold is reached.

Because the device draws current from the V_DD pin to bias all internal circuits, for the best high-speed circuit performance, TI recommends two V_DD bypass capacitors to prevent noise problems. TI highly recommends using surface-mount components. A 0.1-μF ceramic capacitor must be located as close as possible to the V_DD to GND pins of the gate-driver device. In addition, a larger capacitor (such as 1-μF) with relatively low ESR must be connected in parallel and close proximity, in order to help deliver the high-current peaks required by the load. The parallel combination of capacitors presents a low impedance characteristic for the expected current levels and switching frequencies in the application.

Figure 26. Power up Non-Inverting Driver

Figure 27. Power up Inverting Driver

8.3.2 Operating Supply Current

The UCC2752x products feature very low quiescent I_DD currents. The typical operating-supply current in UVLO state and fully on state (under static and switching conditions) are summarized in Figure 5, Figure 6 and Figure 7. The I_DD current when the device is fully on and outputs are in a static state (DC high or DC low, refer Figure 6) represents lowest quiescent I_DD current when all the internal logic circuits of the device are fully operational. The total supply current is the sum of the quiescent I_DD current, the average I_OUT current due to switching and finally any current related to pullup resistors on the enable pins and inverting input pins. For example when the inverting Input pins are pulled low additional current is drawn from V_DD supply through the pullup resistors (refer to Figure 22 though Figure 25). Knowing the operating frequency (f_SW) and the MOSFET gate (Q_G) charge at the drive voltage being used, the average I_OUT current can be calculated as product of Q_G and f_SW.

A complete characterization of the I_DD current as a function of switching frequency at different V_DD bias voltages under 1.8-nF switching load in both channels is provided in Figure 17. The strikingly linear variation and close correlation with theoretical value of average I_OUT indicates negligible shoot-through inside the gate-driver device attesting to its high-speed characteristics.

8.3.3 Input Stage

The input pins of UCC2752x gate-driver devices are based on a TTL and CMOS compatible input-threshold logic that is independent of the V_DD supply voltage. With typically high threshold = 2.1 V and typically low threshold = 1.2 V, the logic level thresholds are conveniently driven with PWM control signals derived from 3.3-V and 5-V digital power-controller devices. Wider hysteresis (typ 0.9 V) offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. UCC2752x devices also feature tight control of the input pin threshold voltage levels which eases system design considerations and ensures stable operation across temperature (refer to Figure 9). The very low input capacitance on these pins reduces loading and increases switching speed.

The UCC2752x devices feature an important safety feature wherein, whenever any of the input pins is in a floating condition, the output of the respective channel is held in the low state. This is achieved using V_DD pullup resistors on all the Inverting inputs (INA, INB in UCC27523, INA in UCC27525 and INA–, INB– in UCC27526) or GND pulldown resistors on all the non-inverting input pins (INA, INB in UCC27524, INB in UCC27525 and INA+, INB+ in UCC27526), as shown in the device block diagrams.

While UCC27523/4/5 devices feature one input pin per channel, the UCC27526 features a dual input configuration with two input pins available to control the output state of each channel. With the UCC27526 device the user has the flexibility to drive each channel using either a non-inverting input pin (INx+) or an inverting input pin (INx–). The state of the output pin is dependent on the bias on both the INx+ and INx– pins (where x = A, B). Once an Input pin is chosen to drive a channel, the other input pin of that channel (the unused input pin) must be properly biased in order to enable the output of the channel. The unused input pin cannot remain in a floating condition because, as mentioned earlier, whenever any input pin is left in a floating condition, the output of that channel is disabled using the internal pullup or pulldown resistors for safety purposes. Alternatively, the unused input pin is used effectively to implement an enable/disable function, as explained below.

• In order to drive the channel x (x = A or B) in a non-inverting configuration, apply the PWM control input signal to INx+ pin. In this case, the unused input pin, INx-, must be biased low (for example, tied to GND) in order to enable the output of this channel.
  • Alternately, the INx– pin can be used to implement the enable/disable function using an external logic signal. OUTx is disabled when INx- is biased High and OUTx is enabled when INX– is biased low.
• In order to drive the channel x (x = A or B) in an Inverting configuration, apply the PWM control input signal to INX– pin. In this case, the unused input pin, INX+, must be biased high (for example, tied to VDD) in order to enable the output of the channel.
  • Alternately, the INX+ pin can be used to implement the enable/disable function using an external logic signal. OUTX is disabled when INX+ is biased low and OUTX is enabled when INX+ is biased high.
• Finally, it is worth noting that the UCC27526 output pin can be driven into high state only when INx+ pin is biased high and INx- input is biased low.

Refer to the input/output logic truth table and typical application diagrams, (Figure 34, Figure 35, and Figure 35), for additional clarification.

The input stage of each driver is driven by a signal with a short rise or fall time. This condition is satisfied in typical power supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (< 200 ns) with a slow changing input voltage, the output of the driver may switch repeatedly at a high frequency. While the wide hysteresis offered in UCC2752x definitely alleviates this concern over most other TTL input threshold devices, extra care is necessary in these implementations. If limiting the rise or fall times to the power device is the primary goal, then TI highly recommends an external resistance between the output of the driver and the power device. This external resistor has the additional benefit of reducing part of the gate-charge related power dissipation in the gate-driver device package and transferring it into the external resistor itself.

8.3.4 Enable Function

The enable function is an extremely beneficial feature in gate-driver devices especially for certain applications such as synchronous rectification where the driver outputs disable in light-load conditions to prevent negative current circulation and to improve light-load efficiency.

UCC27523/4/5 devices are provided with independent enable pins ENx for exclusive control of each driver-channel operation. The enable pins are based on a non-inverting configuration (active-high operation). Thus when ENx pins are driven high the drivers are enabled and when ENx pins are driven low the drivers are disabled. Like the input pins, the enable pins are also based on a TTL and CMOS compatible input-threshold logic that is independent of the supply voltage and are effectively controlled using logic signals from 3.3-V and 5-V microcontrollers. The UCC2752X devices also feature tight control of the Enable-function threshold-voltage levels which eases system design considerations and ensures stable operation across temperature (refer to Figure 10). The ENx pins are internally pulled up to V_DD using pullup resistors as a result of which the outputs of the device are enabled in the default state. Hence the ENx pins are left floating or Not Connected (N/C) for standard operation, where the enable feature is not needed. Essentially, this floating allows the UCC27523/4/5 devices to be pin-to-pin compatible with TI’s previous generation drivers UCC27323/4/5 respectively, where pins 1, 8 are N/C pins. If the Channel A and Channel B inputs and outputs are connected in parallel to increase the driver current capacity, ENA and ENB are connected and driven together.

The UCC27526 device does not feature dedicated enable pins. However, as mentioned earlier, an enable/disable function is easily implemented in UCC27526 using the unused input pin. When INx+ is pulled down to GND or INx– is pulled down to VDD, the output is disabled. Thus INx+ pin is used like an enable pin that is based on active high logic, while INx– is used like an enable pin that is based on active low logic. Note that while the ENA, ENB pins in UCC27523/4/5 are allowed to be in floating condition during standard operation and the outputs will be enabled, the INx+, INx– pins in UCC27526 are not allowed to be floating because this will disable the outputs.

8.3.5 Output Stage

The UCC2752x device output stage features a unique architecture on the pullup structure which delivers the highest peak-source current when it is most needed during the Miller plateau region of the power-switch turnon transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pullup structure features a P-channel MOSFET and an additional N-channel MOSFET in parallel. The function of the N-channel MOSFET is to provide a brief boost in the peak sourcing current enabling fast turnon. This is accomplished by briefly turning-on the N-channel MOSFET during a narrow instant when the output is changing state from Low to High.

Figure 28. UCC2752x Gate Driver Output Structure

The R_OH parameter (see Electrical Characteristics) is a DC measurement and it is representative of the on-resistance of the P-Channel device only. This is because the N-Channel device is held in the off state in DC condition and is turned-on only for a narrow instant when output changes state from low to high. Note that effective resistance of UCC2752x pullup stage during the turnon instant is much lower than what is represented by R_OH parameter.

The pulldown structure in UCC2752x is simply composed of a N-Channel MOSFET. The R_OL parameter (see Electrical Characteristics), which is also a DC measurement, is representative of the impedance of the pulldown stage in the device. In UCC2752x, the effective resistance of the hybrid pullup structure during turnon is estimated to be approximately 1.5 × R_OL, estimated based on design considerations.

Each output stage in UCC2752x can supply 5-A peak source and 5-A peak sink current pulses. The output voltage swings between V_DD and GND providing rail-to-rail operation, thanks to the MOS-output stage which delivers very low drop-out. The presence of the MOSFET-body diodes also offers low impedance to switching overshoots and undershoots which means that in many cases, external Schottky-diode clamps may be eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either damage to the device or logic malfunction.

The UCC2752x devices are particularly suited for dual-polarity, symmetrical drive-gate transformer applications where the primary winding of transformer driven by OUTA and OUTB, with inputs INA and INB being driven complementary to each other. This situation is due to the extremely low drop-out offered by the MOS output stage of these devices, both during high (V_OH) and low (V_OL) states along with the low impedance of the driver output stage, all of which allow alleviate concerns regarding transformer demagnetization and flux imbalance. The low propagation delays also ensure accurate reset for high-frequency applications.

For applications that have zero voltage switching during power MOSFET turnon or turnoff interval, the driver supplies high-peak current for fast switching even though the miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before power MOSFET is switched on.

8.3.6 Low Propagation Delays and Tightly Matched Outputs

The UCC2752x driver devices feature a best in class, 13-ns (typical) propagation delay between input and output which goes to offer the lowest level of pulse-transmission distortion available in the industry for high frequency switching applications. For example in synchronous rectifier applications, the SR MOSFETs are driven with very low distortion when one driver device is used to drive both the SR MOSFETs. Further, the driver devices also feature an extremely accurate, 1-ns (typ) matched internal-propagation delays between the two channels which is beneficial for applications requiring dual gate drives with critical timing. For example in a PFC application, a pair of paralleled MOSFETs may be driven independently using each output channel, which the inputs of both channels are driven by a common control signal from the PFC controller device. In this case the 1ns delay matching ensures that the paralleled MOSFETs are driven in a simultaneous fashion with the minimum of turnon delay difference. Yet another benefit of the tight matching between the two channels is that the two channels are connected together to effectively increase current drive capability, for example A and B channels may be combined into one driver by connecting the INA and INB inputs together and the OUTA and OUTB outputs together. Then, one signal controls the paralleled combination.

Caution must be exercised when directly connecting OUTA and OUTB pins together because there is the possibility that any delay between the two channels during turnon or turnoff may result in shoot-through current conduction as shown in Figure 29. While the two channels are inherently very well matched (4-ns Max propagation delay), note that there may be differences in the input threshold voltage level between the two channels which causes the delay between the two outputs especially when slow dV/dt input signals are employed. TI recommends the following guidelines whenever the two driver channels are paralleled using direct connections between OUTA and OUTB along with INA and INB:

• Use very fast dV/dt input signals (20 V/µs or greater) on INA and INB pins to minimize impact of differences in input thresholds causing delays between the channels.
• INA and INB connections must be made as close to the device pins as possible.

Wherever possible, a safe practice would be to add an option in the design to have gate resistors in series with OUTA and OUTB. This allows the option to use 0-Ω resistors for paralleling outputs directly or to add appropriate series resistances to limit shoot-through current, should it become necessary.

Figure 29. Slow Input Signal May Cause Shoot-Through Between Channels During Paralleling
(Recommended dV/dT is 20 V/Μs or Higher)

Figure 30. Turnon Propagation Delay
(C_L = 1.8 nF, V_DD = 12 V)

Figure 32. Turnoff Propagation Delay
(C_L = 1.8 nF, V_DD = 12 V)

Figure 31. Turnon Rise Time
(C_L = 1.8 nF, V_DD = 12 V)

Figure 33. Turnoff Fall Time
(C_L = 1.8 nF, V_DD = 12 V)

Table 2. Device Logic Table (UCC27523/4/5)

Table 3. Device Logic Table (UCC27526)