Product details

Number of channels (#) 2 Power switch MOSFET, IGBT, GaNFET Peak output current (A) 5 Input VCC (Min) (V) 4.5 Input VCC (Max) (V) 18 Features Enable Pin Operating temperature range (C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Prop delay (ns) 13 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) 0 Rating Catalog Undervoltage lockout (Typ) 4 Driver configuration Dual, Non-Inverting
Number of channels (#) 2 Power switch MOSFET, IGBT, GaNFET Peak output current (A) 5 Input VCC (Min) (V) 4.5 Input VCC (Max) (V) 18 Features Enable Pin Operating temperature range (C) -40 to 140 Rise time (ns) 7 Fall time (ns) 6 Prop delay (ns) 13 Input threshold CMOS, TTL Channel input logic Dual, Non-Inverting Input negative voltage (V) 0 Rating Catalog Undervoltage lockout (Typ) 4 Driver configuration Dual, Non-Inverting
HVSSOP (DGN) 8 9 mm² 3 x 3 PDIP (P) 8 93 mm² 9.81 x 9.43 SOIC (D) 8 19 mm² 4.9 x 3.9 WSON (DSD) 8 9 mm² 3 x 3
  • Industry-Standard Pinout
  • Two Independent Gate-Drive Channels
  • 5-A Peak Source and Sink-Drive Current
  • Independent-Enable Function for Each Output
  • TTL and CMOS Compatible Logic Threshold
    Independent of Supply Voltage
  • Hysteretic-Logic Thresholds for High Noise
    Immunity
  • Inputs and Enable Pin-Voltage Levels Not
    Restricted by VDD Pin Bias Supply Voltage
  • 4.5-V to 18-V Single-Supply Range
  • Outputs Held Low During VDD-UVLO, (Ensures
    Glitch-Free Operation at Power up and Power
    Down)
  • Fast Propagation Delays (13-ns Typical)
  • Fast Rise and Fall Times (7-ns and 6-ns Typical)
  • 1-ns Typical Delay Matching Between Two
    Channels
  • Two Outputs are in Parallel for Higher Drive
    Current
  • Outputs Held Low When Inputs Floating
  • PDIP (8), SOIC (8), MSOP (8) PowerPAD™ and
    3-mm × 3-mm WSON-8 Package Options
  • Operating Temperature Range of –40°C to 140°C
  • Industry-Standard Pinout
  • Two Independent Gate-Drive Channels
  • 5-A Peak Source and Sink-Drive Current
  • Independent-Enable Function for Each Output
  • TTL and CMOS Compatible Logic Threshold
    Independent of Supply Voltage
  • Hysteretic-Logic Thresholds for High Noise
    Immunity
  • Inputs and Enable Pin-Voltage Levels Not
    Restricted by VDD Pin Bias Supply Voltage
  • 4.5-V to 18-V Single-Supply Range
  • Outputs Held Low During VDD-UVLO, (Ensures
    Glitch-Free Operation at Power up and Power
    Down)
  • Fast Propagation Delays (13-ns Typical)
  • Fast Rise and Fall Times (7-ns and 6-ns Typical)
  • 1-ns Typical Delay Matching Between Two
    Channels
  • Two Outputs are in Parallel for Higher Drive
    Current
  • Outputs Held Low When Inputs Floating
  • PDIP (8), SOIC (8), MSOP (8) PowerPAD™ and
    3-mm × 3-mm WSON-8 Package Options
  • Operating Temperature Range of –40°C to 140°C

The UCC2752x family of devices are dual-channel, high-speed, low-side gate-driver devices capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC2752x can deliver high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 13 ns). In addition, the drivers feature matched internal propagation delays between the two channels. These delays are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with one input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

The UCC2752x family provide the combination of three standard logic options – dual inverting, dual noninverting, one inverting and one noninverting driver. UCC27526 features a dual input design which offers flexibility of both inverting (IN– pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN– pin controls the state of the driver output. The unused input pin is used for enable and disable functions. For safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family ensure that outputs are held LOW when input pins are in floating condition. The UCC27523, UCC27524, and UCC27525 devices feature Enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

UCC2752x family of devices are available in SOIC-8 (D), MSOP-8 with exposed pad (DGN) and 3-mm × 3-mm WSON-8 with exposed pad (DSD) packages. UCC27524 is also offered in PDIP-8 (P) package. UCC27526 is only offered in 3-mm × 3-mm WSON (DSD) package.

The UCC2752x family of devices are dual-channel, high-speed, low-side gate-driver devices capable of effectively driving MOSFET and IGBT power switches. Using a design that inherently minimizes shoot-through current, UCC2752x can deliver high-peak current pulses of up to 5-A source and 5-A sink into capacitive loads along with rail-to-rail drive capability and extremely small propagation delay (typically 13 ns). In addition, the drivers feature matched internal propagation delays between the two channels. These delays are very well suited for applications requiring dual-gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two channels in parallel to effectively increase current-drive capability or driving two switches in parallel with one input signal. The input pin thresholds are based on TTL and CMOS compatible low-voltage logic, which is fixed and independent of the VDD supply voltage. Wide hysteresis between the high and low thresholds offers excellent noise immunity.

The UCC2752x family provide the combination of three standard logic options – dual inverting, dual noninverting, one inverting and one noninverting driver. UCC27526 features a dual input design which offers flexibility of both inverting (IN– pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN– pin controls the state of the driver output. The unused input pin is used for enable and disable functions. For safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family ensure that outputs are held LOW when input pins are in floating condition. The UCC27523, UCC27524, and UCC27525 devices feature Enable pins (ENA and ENB) to have better control of the operation of the driver applications. The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.

UCC2752x family of devices are available in SOIC-8 (D), MSOP-8 with exposed pad (DGN) and 3-mm × 3-mm WSON-8 with exposed pad (DSD) packages. UCC27524 is also offered in PDIP-8 (P) package. UCC27526 is only offered in 3-mm × 3-mm WSON (DSD) package.

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Technical documentation

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Type Title Date
* Data sheet UCC2752x Dual 5-A High-Speed, Low-Side Gate Driver datasheet (Rev. G) PDF | HTML 01 Apr 2015
Technical article Managing power-supply noise with a 30-V gate driver 07 Dec 2021
Application note Benefits of a Compact, Powerful, and Robust Low-Side Gate Driver PDF | HTML 10 Nov 2021
More literature Troubleshooting gate drive circuits in automotive and industrial applications 23 Mar 2021
Application note External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Application note Improving Efficiency of DC-DC Conversion through Layout 07 May 2019
Application note How to overcome negative voltage transients on low-side gate drivers' inputs 18 Jan 2019
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 29 Oct 2018
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse 19 Sep 2018
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime 30 May 2018
Technical article Boosting efficiency for your solar inverter designs 24 May 2018
Application note Low-Side Gate Drivers With UVLO Versus BJT Totem-Pole 16 Mar 2018
More literature Design review of a 2-kW parallelable power supply module 17 Aug 2016
More literature Design review of a 2-kW parallelable power supply module (PPT) 17 Aug 2016
More literature Design Review of a Full-Featured 350-W Offline Power Converter 29 Oct 2013

Design & development

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Simulation model

UCC27524 PSpice Transient Model

SLUM243.ZIP (28 KB) - PSpice Model
Simulation model

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Simulation tool

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Calculation tool

UCC2752X Schematic Review Template

SLURB22.ZIP (110 KB)
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Package Pins Download
HVSSOP (DGN) 8 View options
PDIP (P) 8 View options
SOIC (D) 8 View options
SON (DSD) 8 View options

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