SNVSA89A December   2014  – May 2015 UCC27528-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Switching Characteristics
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD and Undervoltage Lockout
      2. 8.3.2 Operating Supply Current
      3. 8.3.3 Input Stage
      4. 8.3.4 Enable Function
      5. 8.3.5 Output Stage
      6. 8.3.6 Low Propagation Delays and Tightly Matched Outputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input-to-Output Logic
        2. 9.2.2.2 Enable and Disable Function
        3. 9.2.2.3 VDD Bias Supply Voltage
        4. 9.2.2.4 Propagation Delay
        5. 9.2.2.5 Drive Current and Power Dissipation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

High-current gate-driver devices are required in switching power applications for a variety of reasons. To implement fast switching in power devices and reduce associated switching power losses, a powerful gate-driver device can be employed between the PWM output of control devices and the gates of the power semiconductor devices.

Furthermore, gate driver devices are indispensable when having the PWM-controller device directly drive the gates of the switching devices is not feasible. With the advent of digital power, this situation is often encountered because the PWM signal from the digital controller is typically a 3.3-V logic signal which is not capable of effectively turning on a power switch. A level shifting circuitry is required to boost the 3.3-V signal to the gate-drive voltage (such as 12 V) to fully turn on the power device and minimize conduction losses. Traditional buffer drive circuits based on NPN and PNP bipolar transistors in totem-pole arrangement are emitter follower configurations. These circuits prove inadequate with digital power because they lack level-shifting capability.

Gate driver devices effectively combine both the level-shifting and buffer drive functions. Gate driver devices also satisfy other needs such as minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the power switch, driving gate drive transformers and controlling floating power device gates which reduces power dissipation and thermal stress in controller devices by moving gate charge power losses into itself. In summary Gate-driver devices are an extremely important component in switching power combining benefits of high performance, low cost, component count, board-space reduction, and simplified system design.

9.2 Typical Application

UCC27528-Q1 typapp1_snvsa89.gifFigure 24. UCC27528-Q1 Typical Application Diagram

9.2.1 Design Requirements

When selecting the proper gate driver device for an end application, some design considerations must be evaluated first to make the most appropriate selection. Among these considerations are input-to-output Logic, enable and disable function, supply voltage (VDD), propagation delay, and power dissipation.

The design requirements include the following:

  • Supply voltage (VDD)
  • Type of input threshold (CMOS or TTL)
  • Propagation delay
  • Delay matching
  • Peak drive current
  • Enable function (whether or not it exists)
  • Operating temperature range

9.2.2 Detailed Design Procedure

9.2.2.1 Input-to-Output Logic

The design should specify which type of input-to-output configuration should be used. The UCC27528-Q1 device can only provide dual non-inverting input-to-output with enable control.

9.2.2.2 Enable and Disable Function

Certain applications demand independent control of the output state of the driver. The UCC27528-Q1 device offers two independent enable pins ENx pins for exclusive control of each driver channels as listed in Table 2. The ENA, ENB pins in the UCC27528-Q1 device can be in the floating condition during standard operation with the outputs enabled.

9.2.2.3 VDD Bias Supply Voltage

The bias supply voltage to be applied to the VDD pin of the device should never exceed the values listed in the Recommended Operating Conditions table. However, different power switches demand different voltage levels to be applied at the gate terminals for effective turnon and turnoff. With certain power switches, a positive gate voltage may be required for turnon and a negative gate voltage may be required for turnoff, in which case the VDD bias supply equals the voltage differential. With a wide operating range from 4.5 V to 18 V, the UCC27528-Q1 device can be used to drive a variety of power switches, such as Si MOSFETs (for example, VGS = 4.5 V, 10V, 12 V), IGBTs (VGE = 15 V, 18 V), and wide-bandgap power semiconductors (such as GaN, certain types of which allow no higher than 6 V to be applied to the gate pins).

9.2.2.4 Propagation Delay

The acceptable propagation delay from the gate driver is dependent on the switching frequency at which it is used and the acceptable level of pulse distortion to the system. The UCC27528-Q1 device features fast 17-ns (typical) propagation delays which ensures very-little pulse distortion and allows operation at very high-frequencies. See the Switching Characteristics table for the propagation and switching characteristics of the UCC27528-Q1 device. For certain application that require programmable propagation delay, The UCC27528-Q1 device can accept slow dv/dt input signals which allows designers to use RCD circuits on the input pin to program propagation as shown in Figure 21.

9.2.2.5 Drive Current and Power Dissipation

The UCC27528-Q1 driver device is capable of delivering 5 A of current to a MOSFET gate for a period of several hundred nanoseconds at VDD = 12 V. High peak current is required to quickly turn on the device. Then, to turn off the device, the driver is required to sink a similar amount of current to ground. This process repeats at the operating frequency of the power device. The power dissipated in the gate-driver device package depends on the following factors:

  • The gate charge required of the power MOSFET (usually a function of the drive voltage VGS, which is very close to input bias supply voltage VDD because of low VOH drop-out)
  • Switching frequency
  • Use of external gate resistors

Because the UCC27528-Q1 device features very-low quiescent currents and internal logic to eliminate any shoot-through in the output driver stage, the effect on the power dissipation within the gate driver can be safely assumed to be negligible.

When a driver device is tested with a discrete, capacitive load, calculating the power that is required from the bias supply fairly simple. Use Equation 2 to calculate the energy that must be transferred from the bias supply to charge the capacitor.

Equation 2. UCC27528-Q1 qu1_lusaq3.gif

where

  • CLOAD is load capacitor
  • VDD is bias voltage feeding the driver

An equal amount of energy is dissipated when the capacitor is charged which leads to a total power loss given by Equation 3.

Equation 3. UCC27528-Q1 qu2_lusaq3.gif

where

  • fSW is the switching frequency

With VDD = 12 V, CLOAD = 10 nF, and fSW = 300 kHz, use Equation 4 to calculate the power loss.

Equation 4. UCC27528-Q1 qu3_snvsa89.gif

The switching load presented by a power MOSFET can be converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge required to swing the drain voltage of the power device as it switches between the ON and OFF states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to switch the device under specified conditions. Use the gate charge Qg to determine the power that must be dissipated when charging a capacitor by using the equivalence Qg = CLOADVDD to provide Equation 5 for power.

Equation 5. UCC27528-Q1 qu4_lusaq3.gif

Assuming that the UCC27528-Q1 device is driving power MOSFET with 60 nC of gate charge (Qg = 60 nC at VDD = 12 V) on each output, use Equation 6 to calculate the gate-charge related power loss.

Equation 6. UCC27528-Q1 qu5_snvsa89.gif

This power, PG, is dissipated in the resistive elements of the circuit when the MOSFET is turned on or off. Half of the total power is dissipated when the load capacitor is charged during turn-on, and the other half is dissipated when the load capacitor is discharged during turn-off. When no external gate resistor is employed between the driver and MOSFET or IGBT, this power is completely dissipated inside the driver package. With the use of external gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component). Based on this simplified analysis, use Equation 7 to calculate the driver power dissipation during switching.

Equation 7. UCC27528-Q1 qu_psw_lusaq3.gif

where

  • ROFF = ROL
  • RON (effective resistance of pullup structure) = 1.5 × ROL

In addition to the previously calculated gate-charge related power dissipation, additional dissipation in the driver is related to the power associated with the quiescent bias current consumed by the device to bias all internal circuits, such as input stage (with pullup and pulldown resistors), enable, and UVLO sections. Referring to Figure 4, the quiescent current is less than 0.6 mA even in the highest case. Use Equation 8 to calculate the quiescent power dissipation.

Equation 8. UCC27528-Q1 qu6_lusaq3.gif

Assuming, IDD = 6 mA, use Equation 9 to calculate the power loss.

Equation 9. UCC27528-Q1 qu7_snvsa89.gif

Clearly, this power loss is insignificant compared to gate-charge related power dissipation that was calculated previously.

With a 12-V supply, the bias current can be estimated as shown in Equation 10, with an additional 0.6-mA overhead for the quiescent consumption:

Equation 10. UCC27528-Q1 qu8_lusaq3.gif

9.2.3 Application Curves

VDD = 5 V, Load = 2 RJK0453DPB (power FET)
UCC27528-Q1 appcurve1_snvsa89.gifFigure 25. Typical Turnon Waveform
UCC27528-Q1 appcurve2_snvsa89.gifFigure 26. Typical Turnoff Waveform