SLUSFS4A September   2025  – September 2025 UCC27734-Q1 , UCC27735-Q1

PRODUCTION DATA  

  1.   1
  2. Features
  3. Applications
  4. Description
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Dynamic Electrical Characteristics
    7. 5.7 Timing Diagrams
    8. 5.8 Typical Characteristics
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Input Stages and Interlock
      2. 6.3.2 Enable Function (UCC277x5-Q1 Only)
      3. 6.3.3 Undervoltage Lockout (UVLO)
      4. 6.3.4 Level Shifter
      5. 6.3.5 Output Stage
      6. 6.3.6 Low Propagation Delays and Tightly Matched Outputs
      7. 6.3.7 HS Node dV/dt
      8. 6.3.8 Split Grounds (COM and VSS)
      9. 6.3.9 Operation Under Negative HS Voltage Condition
    4. 6.4 Device Functional Modes
      1. 6.4.1 Input and Output Logic Table
      2. 6.4.2 Operation Under 100% Duty Cycle Condition
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Selecting HI and LI Low Pass Filter Components (RHI, RLI, CHI, CLI)
        2. 7.2.2.2 Selecting Bootstrap Capacitor (CBOOT)
        3. 7.2.2.3 Selecting VDD Bypass Capacitor (CVDD)
        4. 7.2.2.4 Selecting Bootstrap Resistor (RBOOT)
        5. 7.2.2.5 Selecting Gate Resistor RHO/RLO
        6. 7.2.2.6 Selecting Bootstrap Diode
        7. 7.2.2.7 Estimate the UCC2773x-Q1 Power Losses
        8. 7.2.2.8 Application Example Schematic Note
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
      2. 7.4.2 Layout Example
  9. Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Third-Party Products Disclaimer
      2. 8.1.2 Development Support
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Enable Function (UCC277x5-Q1 Only)

The enable function is a beneficial feature in applications where the controller is located on the secondary side of an isolation barrier, which is common with digital controllers. In these applications, it is easy to turn off the driver signal in a very short time when critical faults such as primary-side overcurrent occurs. The enable function response time is typically around 32ns.

The enable pin controls both the high-side and low-side driver-channel operation. The enable pin is based on a non-inverting configuration (active-high operation). Thus, when EN pin is driven high the driver is enabled and when EN pin is driven low the driver outputs are set low. The EN pin is internally pulled up to VDD using a 200kΩ pull-up resistor, therefore the outputs of the device are enabled in the default state. The EN pin may be connected to VDD, left floating, or Not Connected (N/C) for standard operation, when the enable feature is not needed. Care must be taken not to connect the EN pin to ground, which permanently disables the device. Like the input pins, the enable pin is also based on a TTL and CMOS compatible input-threshold logic that is independent of the supply voltage and is effectively controlled using logic signal from 3.3V and 5V microcontrollers. The UCC2773x-Q1 also features tight control of the enable-function-threshold voltage levels which eases system design considerations and ensures stable operation across temperature.