SLUS168E Apr   1999  – August 2015 UCC2808-1 , UCC2808-2 , UCC3808-1 , UCC3808-2

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Pin Descriptions
    4. 7.4 Device Functional Modes
      1. 7.4.1 VCC
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The UCCx808-x device is a highly-integrated, low power current mode push-pull PWM controller. The controller employs low starting current, and employs an internal control algorithm that offers accurate static output voltage regulation against line and load. The UCCx808-x family offers a variety of package temperature range options, and choice of undervoltage lockout levels. The family has UVLO thresholds and hysteresis options for offline and battery-powered system.

Table 1. Undervoltage Lockout Levels

PART NUMBER TURN ON THRESHOLD TURN OFF THRESHOLD
UCCx808-1 12.5 V 8.3 V
UCCx808-2 4.3 V 4.1 V

Table 2. Undervoltage Lockout Options

TA = TJ PACKAGED DEVICES
UVLO OPTION SOIC (D) PDIP (N)
–40°C to 85°C 12.5 V/8.3 V UCC2808D-1 UCC2808N-1
4.3 V/4.1 V UCC2808D-2 UCC2808N-2
0°C to 70°C 12.5 V/8.3 V UCC3808D-1 UCC3808N-1
4.3 V/4.1 V UCC3808D-2 UCC3808N-2

7.2 Functional Block Diagram

UCC2808-1 UCC2808-2 UCC3808-1 UCC3808-2 block_diagram_slus168.gif
Pinout shown is for SOIC and PDIP packages.
Figure 4. Functional Block Diagram
UCC2808-1 UCC2808-2 UCC3808-1 UCC3808-2 block_diagram_for_oscillator_slus168.gif
The oscillator generates a sawtooth waveform on RC. During the RC rise time, the output stages alternate on time, but both stages are off during the RC fall time. The output stages switch at ½ the oscillator frequency, with guaranteed duty cycle of <50% for both outputs.
Figure 5. Block Diagram for Oscillator

7.3 Feature Description

7.3.1 Pin Descriptions

COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier in the UCC3808 is a true low-output impedance, 2-MHz operational amplifier. As such, the COMP pin can both source and sink current. However, the error amplifier is internally current limited, so that zero duty cycle can be externally forced by pulling COMP to GND.

The UCC3808 family features built-in full cycle soft-start. Soft-start is implemented as a clamp on the maximum COMP voltage.

CS: The input to the PWM, peak current, and overcurrent comparators. The overcurrent comparator is only intended for fault sensing. Exceeding the overcurrent threshold will cause a soft-start cycle.

FB: The inverting input to the error amplifier. For best stability, keep FB lead length as short as possible and FB stray capacitance as small as possible.

GND: Reference ground and power ground for all functions. Due to high currents, and high frequency operation of the UCC3808, a low impedance circuit board ground plane is highly recommended.

OUTA and OUTB: Alternating high current output stages. Both stages are capable of driving the gate of a power MOSFET. Each stage is capable of 500-mA peak source current, and 1-A peak sink current.

The output stages switch at half the oscillator frequency, in a push/pull configuration. When the voltage on the RC pin is rising, one of the two outputs is high, but during fall time, both outputs are off. This dead time between the two outputs, along with a slower output rise time than fall time, insures that the two outputs can not be on at the same time. This dead time is typically 60 ns to 200 ns and depends upon the values of the timing capacitor and resistor.

The high-current output drivers consist of MOSFET output devices, which switch from VDD to GND. Each output stage also provides a very low impedance to overshoot and undershoot. This means that in many cases, external schottky clamp diodes are not required.

RC: The oscillator programming pin. The oscillator of the UCC3808-x tracks VDD and GND internally, so that variations in power supply rails minimally affect frequency stability. Figure 5 shows the oscillator block diagram.

Only two components are required to program the oscillator: a resistor (tied to the VDD and RC), and a capacitor (tied to the RC and GND). The approximate oscillator frequency is determined by the simple formula:

Equation 1. UCC2808-1 UCC2808-2 UCC3808-1 UCC3808-2 equation_02_slus168.gif

where

  • frequency is in hertz, resistance in ohms, and capacitance in farads.

The recommended range of timing resistors is between 10 kΩ and 200 kΩ and range of timing capacitors is between 100 pF and 1000 pF. Timing resistors less than 10 kΩ must be avoided.

For best performance, keep the timing capacitor lead to GND as short as possible, the timing resistor lead from VDD as short as possible, and the leads between timing components and RC as short as possible. Separate ground and VDD traces to the external timing network are encouraged.

VDD: The power input connection for this device. Although quiescent VDD current is very low, total supply current will be higher, depending on OUTA and OUTB current, and the programmed oscillator frequency. Total VDD current is the sum of quiescent VDD current and the average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT current can be calculated from:

Equation 2. IOUT = Qg F

where

  • F is frequency To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible along with an electrolytic capacitor.

A 1-μF decoupling capacitor is recommended.

7.4 Device Functional Modes

7.4.1 VCC

When VCC becomes above 12.5 V (for UCCx808-1) or 4.3 V (for UCCx808-2), the device is enable, and after all fault conditions are cleared, the gate driver starts with soft-start. When VCC drops below 8.3 V (for UCCx808-1) or 4.1 V (for UCCx808-2), the device enters the UVLO protection mode and both gate drivers are actively pulled low.