SLUSB86C November   2012  – June 2017 UCC28710 , UCC28711 , UCC28712 , UCC28713

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Detailed Pin Description
        1. 8.3.1.1 VDD (Device Bias Voltage Supply)
        2. 8.3.1.2 GND (Ground)
        3. 8.3.1.3 VS (Voltage-Sense)
        4. 8.3.1.4 DRV (Gate Drive)
        5. 8.3.1.5 CS (Current Sense)
        6. 8.3.1.6 CBC (Cable Compensation), Pin 1 UCC28700
        7. 8.3.1.7 NTC (NTC Thermistor Shut-down), Pin 1 UCC28701/2/3
      2. 8.3.2 Fault Protection
    4. 8.4 Device Functional Modes
      1. 8.4.1 Primary-Side Voltage Regulation
      2. 8.4.2 Primary-Side Current Regulation
      3. 8.4.3 Valley Switching
      4. 8.4.4 Start-Up Operation
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Stand-by Power Estimate
        3. 9.2.2.3 Input Bulk Capacitance and Minimum Bulk Voltage
        4. 9.2.2.4 Transformer Turns Ratio, Inductance, Primary-Peak Current
        5. 9.2.2.5 Transformer Parameter Verification
        6. 9.2.2.6 Output Capacitance
        7. 9.2.2.7 VDD Capacitance, CDD
        8. 9.2.2.8 VS Resistor Divider, Line Compensation, and Cable Compensation
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
      2. 12.1.2 Device Nomenclature
        1. 12.1.2.1  Capacitance Terms in Farads
        2. 12.1.2.2  Duty Cycle Terms
        3. 12.1.2.3  Frequency Terms in Hertz
        4. 12.1.2.4  Current Terms in Amperes
        5. 12.1.2.5  Current and Voltage Scaling Terms
        6. 12.1.2.6  Transformer Terms
        7. 12.1.2.7  Power Terms in Watts
        8. 12.1.2.8  Resistance Terms in Ω
        9. 12.1.2.9  Timing Terms in Seconds
        10. 12.1.2.10 Voltage Terms in Volts
        11. 12.1.2.11 AC Voltage Terms in VRMS
        12. 12.1.2.12 Efficiency Terms
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
      2. 12.2.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|7
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

Application Information

The UCC2871x family of flyback power supply controllers provides constant voltage (CV) and constant current (CC) output regulation to help meet USB-compliant adaptors and charger requirements. These devices use the information obtained from auxiliary winding sensing (VS) to control the output voltage and do not require optocoupler/TL431 feedback circuitry. Eliminating the optocoupler feedback reduces component count and makes the design more cost effective. Refer to Figure 20 for details.

Typical Application

The procedure in the Detailed Design Procedure section outlines the steps to design a constant-voltage, constant-current flyback converter using the UCC2871x family of controllers. Refer to the typical application schematic for component location (Figure 20) and the Device Nomenclature section for variable definitions.

UCC28710 UCC28711 UCC28712 UCC28713 example_lusb86.gif Figure 20. Design Procedure Application Example

Design Requirements

Table 1. Design Parameters

PARAMETER NOTES AND CONDITIONS MIN NOM MAX UNIT
INPUT CHARACTERISTICS
VIN Input Voltage 100 115/230 240 V
fLINE Line Frequency 47 50/60 64 Hz
PSB_CONV No Load Input Power VIN = Nom, IO = 0 A 10 mW
VIN(RUN) Brownout Voltage IO = Nom 70 V
OUTPUT CHARACTERISTICS
VO Output Voltage VIN = Nom, IO = Nom 4.75 5 5.25 V
VRIPPLE Output Voltage Ripple VIN = Nom, IO = Max 0.1 V
IO Output Current VIN = Min to Max 1 1.05 A
VOVP Output OVP IOUT = Min to Max 5.75 V
Transient Response
V Load Step (VO = 4.1 V to 6 V) (0.1 to 0.6 A) or (0.6 to 0.1 A)
V = 0.9 V for COUT calculation in applications section
4.1 5 6 A
SYSTEMS CHARACTERISTICS
Switching Frequency 90 kHz
η Full Load Efficiency (115/230 V RMS Input) IO = 1 A 74% 76%

Detailed Design Procedure

Custom Design With WEBENCH® Tools

Click here to create a custom design using the UCC28710 device with the WEBENCH® Power Designer.

  1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
  2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
  3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time pricing and component availability.

In most cases, these actions are available:

  • Run electrical simulations to see important waveforms and circuit performance
  • Run thermal simulations to understand board thermal performance
  • Export customized schematic and layout into popular CAD formats
  • Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

Stand-by Power Estimate

Assuming no-load stand-by power is a critical design parameter, determine estimated no-load power based on target converter maximum switching frequency and output power rating.

The following equation estimates the stand-by power of the converter.

Equation 7. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Psb_conv_lusb41.gif

For a typical USB charger application, the bias power during no-load is approximately 2.5 mW. This is based on 25-V VDD and 100-µA bias current. The output preload resistor can be estimated by VOCV and the difference in the converter stand-by power and the bias power. The equation for output preload resistance accounts for bias power estimated at 2.5 mW.

Equation 8. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Rpl_lusb41.gif

The capacitor bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement, typically 325 VDC.

For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the converter stand-by power loss.

Equation 9. UCC28710 UCC28711 UCC28712 UCC28713 qu9_lusb86.gif

Input Bulk Capacitance and Minimum Bulk Voltage

Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency, minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance requirement.

Maximum input power is determined based on VOCV, IOCC, and the full-load efficiency target.

Equation 10. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Pin_lusb41.gif

The below equation provides an accurate solution for input capacitance based on a target minimum bulk capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance.

Equation 11. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Cbulk_lusb41.gif

Transformer Turns Ratio, Inductance, Primary-Peak Current

The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at full load, the minimum input capacitor bulk voltage, and the estimated DCM resonant time.

Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have an estimate from previous designs. For the transition mode operation limit, the period required from the end of secondary current conduction to the first valley of the VDS voltage is ½ of the DCM resonant period, or 1 µs assuming 500-kHz resonant frequency. DMAX can be determined using the equation below.

Equation 12. UCC28710 UCC28711 UCC28712 UCC28713 q_dmax_lusb88.gif

Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation below. DMAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It is set internally by the UCC2871x family at 0.425. The total voltage on the secondary winding needs to be determined; which is the sum of VOCV, the secondary rectifier VF, and the cable compensation voltage (VOCBC). For the 5-V USB charger applications, a turns ratio range of 13 to 15 is typically used.

Equation 13. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Npsmax_lusb41.gif

Once an optimum turns ratio is determined from a detailed transformer design, use this ratio for the following parameters.

The UCC2871x family constant-current regulation is achieved by maintaining a maximum DMAG duty cycle of 0.425 at the maximum primary current setting. The transformer turns ratio and constant-current regulating voltage determine the current sense resistor for a target constant current.

Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias power ratio to rated output power. For a 5-V, 1-A charger example, bias power of 1.5% is a good estimate. An overall transformer efficiency of 0.9 is a good estimate to include 3.5% leakage inductance, 5% core and winding loss, and 1.5% bias power.

Equation 14. UCC28710 UCC28711 UCC28712 UCC28713 qu14_lusb86.gif

The primary transformer inductance can be calculated using the standard energy storage equation for flyback transformers. Primary current, maximum switching frequency and output and transformer power losses are included in the equation below. Initially determine transformer primary current.

Primary current is simply the maximum current sense threshold divided by the current sense resistance.

Equation 15. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Ippmax_lusb41.gif
Equation 16. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Lp_lusb41.gif

The secondary winding to auxiliary winding transformer turns ratio (NAS) is determined by the lowest target operating output voltage in constant-current regulation and the VDD UVLO of the UCC2871x family. There is additional energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns ratio to be used in many designs.

Equation 17. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Nas_lusb41.gif

Transformer Parameter Verification

The transformer turns ratio selected affects the MOSFET VDS and secondary rectifier reverse voltage so these should be reviewed. The UCC2871x family does require a minimum on time of the MOSFET (tON) and minimum DMAG time (tDMAG) of the secondary rectifier in the high line, minimum load condition. The selection of fMAX, LP and RCS affects the minimum tON and tDMAG.

The secondary rectifier and MOSFET voltage stress can be determined by the equations below.

Equation 18. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Vrev_lusb41.gif

For the MOSFET VDS voltage stress, an estimated leakage inductance voltage spike (VLK) needs to be included.

Equation 19. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Vdspk_lusb41.gif

Equation 20 and Equation 21 are used to determine if the minimum tON target of 300 ns and minimum tDMAG target of 1.2 µs is achieved.

Equation 20. UCC28710 UCC28711 UCC28712 UCC28713 q_tonmin_lusb88.gif
Equation 21. UCC28710 UCC28711 UCC28712 UCC28713 q_tdmagmin_lusb88.gif

Output Capacitance

The output capacitance value is typically determined by the transient response requirement from no-load. For example, in some USB charger applications there is a requirement to maintain a minimum VO of 4.1 V with a load-step transient of 0 mA to 500 mA . The equation below assumes that the switching frequency can be at the UCC2871x family's minimum of fSW(min).

Equation 22. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Cout_lusb41.gif

Another consideration of the output capacitor(s) is the ripple voltage requirement which is reviewed based on secondary peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in the equation below.

Equation 23. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Resr_lusb41.gif

VDD Capacitance, CDD

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage in constant-current regulation. At this time the auxiliary winding can sustain the voltage to the UCC2871x family. The total output current available to the load and to charge the output capacitors is the constant-current regulation target. The equation below assumes the output current of the flyback is available to charge the output capacitance until the minimum output voltage is achieved. There is an estimated 1 mA of gate-drive current in the equation and 1 V of margin added to VDD.

Equation 24. UCC28710 UCC28711 UCC28712 UCC28713 qu24_lusb86.gif

VS Resistor Divider, Line Compensation, and Cable Compensation

The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV operation. RS1 is initially determined based on transformer auxiliary to primary turns ratio and desired input voltage operating threshold.

Equation 25. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Rs1_lusb41.gif

The low-side VS pin resistor is selected based on desired VO regulation voltage.

Equation 26. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Rs2_lusb41.gif

The UCC2871x family can maintain tight constant-current regulation over input line by utilizing the line compensation feature. The line compensation resistor (RLC) value is determined by current flowing in RS1 and expected gate drive and MOSFET turnoff delay. Assume a 50-ns internal delay in the UCC2871x family.

Equation 27. UCC28710 UCC28711 UCC28712 UCC28713 q_rlc_lusb88.gif

On the UCC28710, which has adjustable cable compensation, the resistance for the desired compensation level at the output terminals can be determined using Equation 28.

Equation 28. UCC28710 UCC28711 UCC28712 UCC28713 q_dp_Rcbc_lusb41.gif

Application Curves

UCC28710 UCC28711 UCC28712 UCC28713 Figure22.gif Figure 21. Efficiency
UCC28710 UCC28711 UCC28712 UCC28713 Figure24_0907122.gif Figure 23. Output at Startup at 115-V RMS
(5-Ω Load)
UCC28710 UCC28711 UCC28712 UCC28713 Figure26.gif
Figure 25. Output at Startup at 230-V RMS
(5-Ω Load)
UCC28710 UCC28711 UCC28712 UCC28713 Figure28_0910122.gif
CH1 = IO, CH4 = VO With a 5-V Offset
Figure 27. Load Transients:
(0.6-A to 0.1-A Load Step)
UCC28710 UCC28711 UCC28712 UCC28713 Figure23_0907121.gif
Figure 22. Output at Startup at 115-V RMS
(No Load)
UCC28710 UCC28711 UCC28712 UCC28713 Figure25_0907123.gif Figure 24. Output at Startup at 230-V RMS
(No Load)
UCC28710 UCC28711 UCC28712 UCC28713 Figure27_0910121.gif
CH1 = IO, CH4 = VO With a 5-V Offset
Figure 26. Load Transients:
(0.1-A to 0.6-A Load Step)
UCC28710 UCC28711 UCC28712 UCC28713 Figure 11_ 02151218.png
CH4 = VO, Output voltage at EVM output
CH2 = VO, Output voltage measured at the end of the 3M of cable in parallel with a 1-uF capacitor. The output voltage has less than 50 mV of output ripple at the end of the cable.
Figure 28. Output Ripple Voltage at Full Load