SLUSBE8B May   2013  – September 2015 UCC28720


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Detailed Pin Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 Primary-Side Voltage Regulation
      2. 7.4.2 Primary-Side Current Regulation
      3. 7.4.3 Valley Switching
      4. 7.4.4 Start-Up Operation
      5. 7.4.5 Fault Protection
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. Stand-by Power Estimate
        2. Input Bulk Capacitance and Minimum Bulk Voltage
        3. Transformer Turns Ratio, Inductance, Primary-Peak Current
        4. Transformer Parameter Verification
        5. Output Capacitance
        6. VDD Capacitance, CDD
        7. VS Resistor Divider, Line Compensation, and Cable Compensation
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. Definition of Terms
          1.  Capacitance Terms in Farads
          2.  Duty Cycle Terms
          3.  Frequency Terms in Hertz
          4.  Current Terms in Amperes
          5.  Current and Voltage Scaling Terms
          6.  Transformer Terms
          7.  Power Terms in Watts
          8.  Resistance Terms in Ω
          9.  Timing Terms in Seconds
          10. Voltage Terms in Volts
          11. AC Voltage Terms in VRMS
          12. Efficiency Terms
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation


Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The UCC28720 flyback power supply controller provides constant voltage (CV) and constant current (CC) output regulation to help meet USB-compliant adaptors and charger requirements. This device uses the information obtained from auxiliary winding sensing (VS) to control the output voltage and does not require optocoupler/TL431 feedback circuitry. Not requiring optocoupler feedback reduces the component count and makes the design more cost effective and efficient.

8.2 Typical Application

UCC28720 v13092_lusbe8.gif Figure 20. Design Procedure Application Example

8.2.1 Design Requirements

The design parameters are listed in Table 1.

Table 1. Design Parameters

VIN RMS Input Voltage 100 (VIN(MIN)) 115/230 240 V
fLINE Line Frequency 47 50/60 64 Hz
PSB_CONV No Load Input Power VIN = Nom, IOUT = 0 A 10 mW
VIN(RUN) Brownout Voltage IOUT = Nom 70 V
VOCV Output Voltage VIN = Nom, IOUT = NOM 4.75 5 5.25 V
VRIPPLE Output Voltage Ripple VIN = Nom, IO = Max 0.1 V
IOUT Output Current VIN = Min to Max 1 1.05 A
Output OVP IOUT = Min to Max 5.75 V
Transient Response
Load Step (ITRAN = 0.6 A) (0.1 to 0.6 A) or (0.6 to 0.1 A)
V= 0.9 V for Calculations
4.1 5 5 V
fMAX Switching Frequency 70 kHz
ƞ Full Load Efficiency (115/230 V RMS input) IOUT = 1 A 74%

8.2.2 Detailed Design Procedure

This procedure outlines the steps to design a constant-voltage, constant-current flyback converter using the UCC28720 controller. Refer to the Figure 20 for component names and network locations. The design procedure equations use terms that are defined below. Stand-by Power Estimate

Assuming no-load stand-by power is a critical design parameter, determine estimated no-load power based on target converter maximum switching frequency and output power rating.

The following equation estimates the stand-by power of the converter.

Equation 7. UCC28720 q_dp_Psb_conv_lusb41.gif

For a typical USB charger application, the bias power during no-load is approximately 2.5 mW. This is based on 25-V VDD and 100-µA bias current. The output preload resistor can be estimated by VOCV and the difference in the converter stand-by power and the bias power. The equation for output preload resistance accounts for bias power estimated at 2.5 mW.

Equation 8. UCC28720 q_dp_Rpl_lusb41.gif

The capacitor bulk voltage for the loss estimation is the highest voltage for the stand-by power measurement, typically 325 VDC.

For the total stand-by power estimation add an estimated 2.5 mW for snubber loss to the converter stand-by power loss.

Equation 9. UCC28720 qu9_lusb86.gif Input Bulk Capacitance and Minimum Bulk Voltage

Determine the minimum voltage on the input capacitance, CB1 and CB2 total, in order to determine the maximum Np to Ns turns ratio of the transformer. The input power of the converter based on target full-load efficiency, minimum input RMS voltage, and minimum AC input frequency are used to determine the input capacitance requirement.

Maximum input power is determined based on VOCV, IOCC, and the full-load efficiency target.

Equation 10. UCC28720 q_dp_Pin_lusb41.gif

The below equation provides an accurate solution for input capacitance based on a target minimum bulk capacitor voltage. To target a given input capacitance value, iterate the minimum capacitor voltage to achieve the target capacitance.

Equation 11. UCC28720 q_dp_Cbulk_lusb41.gif Transformer Turns Ratio, Inductance, Primary-Peak Current

The maximum primary-to-secondary turns ratio can be determined by the target maximum switching frequency at full load, the minimum input capacitor bulk voltage, and the estimated DCM quasi-resonant time.

Initially determine the maximum available total duty cycle of the on time and secondary conduction time based on target switching frequency and DCM resonant time. For DCM resonant time, assume 500 kHz if you do not have an estimate from previous designs. For the transition mode operation limit, the period required from the end of secondary current conduction to the first valley of the VCE voltage is ½ of the DCM resonant period, or 1 µs assuming 500-kHz resonant frequency. DMAX can be determined using the equation below.

Equation 12. UCC28720 q_dmax_lusb88.gif

Once DMAX is known, the maximum turns ratio of the primary to secondary can be determined with the equation below. DMAGCC is defined as the secondary diode conduction duty cycle during constant-current, CC, operation. It is set internally by the UCC28720 at 0.425. The total voltage on the secondary winding needs to be determined; which is the sum of VOCV, the secondary rectifier VF, and the cable compensation voltage (VOCBC). For the 5-V USB charger applications, a turns ratio range of 13 to 15 is typically used.

Equation 13. UCC28720 q_dp_Npsmax_lusb41.gif

Once an optimum turns ratio is determined from a detailed transformer design, use this ratio for the following parameters.

The UCC28720 constant-current regulation is achieved by maintaining a maximum DMAG duty cycle of 0.425 at the maximum primary current setting. The transformer turns ratio and constant-current regulating voltage determine the current sense resistor for a target constant current.

Since not all of the energy stored in the transformer is transferred to the secondary, a transformer efficiency term is included. This efficiency number includes the core and winding losses, leakage inductance ratio, and bias power ratio to rated output power. For a 5-V, 1-A charger example, bias power of 1.5% is a good estimate. An overall transformer efficiency of 0.9 is a good estimate to include 3.5% leakage inductance, 5% core and winding loss, and 1.5% bias power.

Equation 14. UCC28720 qu14_lusb86.gif

The primary transformer inductance can be calculated using the standard energy storage equation for flyback transformers. Primary current, maximum switching frequency and output and transformer power losses are included in the equation below. Initially determine transformer primary current.

Primary current is simply the maximum current sense threshold divided by the current sense resistance.

Equation 15. UCC28720 q_dp_Ippmax_lusb41.gif
Equation 16. UCC28720 q_dp_Lp_lusb41.gif

The secondary winding to auxiliary winding transformer turns ratio (NAS) is determined by the lowest target operating output voltage in constant-current regulation and the VDD UVLO of the UCC28720. There is additional energy supplied to VDD from the transformer leakage inductance energy which allows a lower turns ratio to be used in many designs.

Equation 17. UCC28720 q_dp_Nas_lusb41.gif Transformer Parameter Verification

The transformer turns ratio selected affects the transistor VC and secondary rectifier reverse voltage so these should be reviewed. The UCC28720 does require a minimum on time of the transistor (tON) and minimum DMAG time (tDMAG) of the secondary rectifier in the high line, minimum load condition. The selection of fMAX, LP and RCS affects the minimum tON and tDMAG.

The secondary rectifier and transistor voltage stress can be determined by the equations below.

Equation 18. UCC28720 q_dp_Vrev_lusb41.gif

For the transistor VC voltage stress, an estimated leakage inductance voltage spike (VLK) needs to be included.

Equation 19. UCC28720 eq_VCPK_SLUSBE8.gif

Equation 20 and Equation 21 are used to determine if the minimum tON target of 300 ns and minimum tDMAG target of 1.2 µs is achieved.

Equation 20. UCC28720 q_tonmin_lusb88.gif
Equation 21. UCC28720 q_tdmagmin_lusb88.gif Output Capacitance

The output capacitance value is typically determined by the transient response requirement from no-load. For example, in some USB charger applications there is a requirement to maintain a minimum VO of 4.1 V with a load-step transient of 0 mA to 500 mA . The equation below assumes that the switching frequency can be at the UCC28720 minimum of fSW(min).

Equation 22. UCC28720 q_dp_Cout_lusb41.gif

Another consideration of the output capacitor(s) is the ripple voltage requirement which is reviewed based on secondary peak current and ESR. A margin of 20% is added to the capacitor ESR requirement in the equation below.

Equation 23. UCC28720 q_dp_Resr_lusb41.gif VDD Capacitance, CDD

The capacitance on VDD needs to supply the device operating current until the output of the converter reaches the target minimum operating voltage in constant-current regulation. At this time the auxiliary winding can sustain the voltage to the UCC28720. The total output current available to the load and to charge the output capacitors is the constant-current regulation target. The equation below assumes the output current of the flyback is available to charge the output capacitance until the minimum output voltage is achieved. There is 1 V of margin added to VDD in the calculation.

Equation 24. UCC28720 qu_24_lusbe8.gif VS Resistor Divider, Line Compensation, and Cable Compensation

The VS divider resistors determine the output voltage regulation point of the flyback converter, also the high-side divider resistor (RS1) determines the line voltage at which the controller enables continuous DRV operation. RS1 is initially determined based on transformer auxiliary to primary turns ratio and desired input voltage operating threshold.

Equation 25. UCC28720 q_dp_Rs1_lusb41.gif

The low-side VS pin resistor is selected based on desired VO regulation voltage.

Equation 26. UCC28720 q_dp_Rs2_lusb41.gif

The UCC28720 can maintain tight constant-current regulation over input line by utilizing the line compensation feature. The line compensation resistor (RLC) value is determined by current flowing in RS1 and expected base drive and transistor turn-off delay. Assume a 50-ns internal delay in the UCC28720.

Equation 27. UCC28720 q_rlc_lusb88.gif

The UCC28720 has adjustable cable drop compensation. The resistance for the desired compensation level at the output terminals can be determined using Equation 28.

Equation 28. UCC28720 q_dp_Rcbc_lusb41.gif

8.2.3 Application Curves

UCC28720 C013_SLUSBE8.png Figure 21. Efficiency
UCC28720 Out_Start_115V_5_Ohm_Load_SLUSBE8.gif Figure 23. Output at Start-up 115-V RMS, 5-Ω Load
UCC28720 Out_Start_230V_5_Ohm_Load_SLUSBE8.gif Figure 25. Output at Start-up 230-V RMS, 5-Ω Load
UCC28720 Load_Trans_0p6_to_0p1_SLUSBE8.gif


CH4 = VOCV with 5-V offset, CH1 = IOUT
Figure 27. Load Transient (0.6- to 0.1-A Load Step)
UCC28720 Out_Start_115V_No_Load_SLUSBE8.gif Figure 22. Output at Start-up 115-V RMS, No Load
UCC28720 Out_Start_230V_No_Load_SLUSBE8.gif Figure 24. Output at Start-up 230-V RMS, No Load
UCC28720 Load_Trans_0p1_to_0p6_SLUSBE8.gif


CH4 = VOCV with 5-V offset, CH1 = IOUT
Figure 26. Load Transients (0.1- to 0.6-A Load Step)
UCC28720 Out_Ripple_SLUSBE8.gif


Ch2 = VOCV at the end of 3M cable and 1 µF of capacitance.
The output ripple at the end of the cables is less than 50 mV.
Figure 28. Output Ripple CH4 = VOCV at Supply Output