SLUSEP2 December   2021 UCC28781

PRODUCTION DATA  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Detailed Pin Description
      1. 7.3.1  BUR Pin (Programmable Burst Mode)
      2. 7.3.2  FB Pin (Feedback Pin)
      3. 7.3.3  REF Pin (Internal 5-V Bias)
      4. 7.3.4  VDD Pin (Device Bias Supply)
      5. 7.3.5  P13 and SWS Pins
      6. 7.3.6  S13 Pin
      7. 7.3.7  IPC Pin (Intelligent Power Control Pin)
      8. 7.3.8  RUN Pin (Driver and Bias Source for Isolator)
      9. 7.3.9  PWMH and AGND Pins
      10. 7.3.10 PWML and PGND Pins
      11. 7.3.11 SET Pin
      12. 7.3.12 RTZ Pin (Sets Delay for Transition Time to Zero)
      13. 7.3.13 RDM Pin (Sets Synthesized Demagnetization Time for ZVS Tuning)
      14. 7.3.14 XCD Pin
      15. 7.3.15 CS, VS, and FLT Pins
    4. 7.4 Device Functional Modes
      1. 7.4.1  Adaptive ZVS Control with Auto-Tuning
      2. 7.4.2  Dead-Time Optimization
      3. 7.4.3  EMI Dither and Dither Fading Function
      4. 7.4.4  Control Law Across Entire Load Range
      5. 7.4.5  Adaptive Amplitude Modulation (AAM)
      6. 7.4.6  Adaptive Burst Mode (ABM)
      7. 7.4.7  Low Power Mode (LPM)
      8. 7.4.8  First Standby Power Mode (SBP1)
      9. 7.4.9  Second Standby Power Mode (SBP2)
      10. 7.4.10 Startup Sequence
      11. 7.4.11 Survival Mode of VDD (INT_STOP)
      12. 7.4.12 System Fault Protections
        1. 7.4.12.1  Brown-In and Brown-Out
        2. 7.4.12.2  Output Over-Voltage Protection (OVP)
        3. 7.4.12.3  Input Overvoltage Protection (IOVP)
        4. 7.4.12.4  Over-Temperature Protection (OTP) on FLT Pin
        5. 7.4.12.5  Over-Temperature Protection (OTP) on CS Pin
        6. 7.4.12.6  Programmable Over-Power Protection (OPP)
        7. 7.4.12.7  Peak Power Limit (PPL)
        8. 7.4.12.8  Output Short-Circuit Protection (SCP)
        9. 7.4.12.9  Over-Current Protection (OCP)
        10. 7.4.12.10 External Shutdown
        11. 7.4.12.11 Internal Thermal Shutdown
      13. 7.4.13 Pin Open/Short Protections
        1. 7.4.13.1 Protections on CS pin Fault
        2. 7.4.13.2 Protections on P13 pin Fault
        3. 7.4.13.3 Protections on RDM and RTZ pin Faults
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application Circuit
      1. 8.2.1 Design Requirements for a 60-W, 15-V ZVSF Bias Supply Application with a DC Input
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Bulk Capacitance and Minimum Bulk Voltage
        2. 8.2.2.2 Transformer Calculations
          1. 8.2.2.2.1 Primary-to-Secondary Turns Ratio (NPS)
          2. 8.2.2.2.2 Primary Magnetizing Inductance (LM)
          3. 8.2.2.2.3 Primary Winding Turns (NP)
          4. 8.2.2.2.4 Secondary Winding Turns (NS)
          5. 8.2.2.2.5 Auxiliary Winding Turns (NA)
          6. 8.2.2.2.6 Winding and Magnetic Core Materials
        3. 8.2.2.3 Calculation of ZVS Sensing Network
        4. 8.2.2.4 Calculation of BUR Pin Resistances
        5. 8.2.2.5 Calculation of Compensation Network
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1  General Considerations
      2. 10.1.2  RDM and RTZ Pins
      3. 10.1.3  SWS Pin
      4. 10.1.4  VS Pin
      5. 10.1.5  BUR Pin
      6. 10.1.6  FB Pin
      7. 10.1.7  CS Pin
      8. 10.1.8  AGND Pin
      9. 10.1.9  PGND Pin
      10. 10.1.10 Thermal Pad
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Receiving Notification of Documentation Updates
    2. 11.2 Support Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.4.12.4 Over-Temperature Protection (OTP) on FLT Pin

The UCC28781 uses an external NTC resistor (RNTC) tied to the FLT pin to program a thermal shutdown temperature near the hotspot of the converter. The NTC shutdown threshold (VNTCTH) of 0.5 V with an internal 50-μA current source flowing through RNTC results in a 10-kΩ thermistor shutdown threshold. If the NTC resistance stays lower than 10 kΩ for more than 50 μs, an OTP fault event is triggered. The 50-μs delay (tFLT(NTC)) allows a filter capacitor (CFLT) to be placed between the FLT pin and the AGND pin, when the NTC resistor is located far away from the controller but close to the hot spot. To avoid the OTP fault from false trigger as RUN goes high, CFLT should be designed to allow VFLT increased above VNTCTH within tFLT(NTC). On the other hand, if the NTC resistor is close to the controller and there is no potential noise coupling path to the sensing traces, CFLT is not needed.

For recovery, the 0.5-V threshold is increased to 1.15 V after the OTP fault, so the NTC resistance must increase above 23 kΩ to reset the OTP fault. This threshold change provides a safe temperature hysteresis to help the hot-spot temperature cool down before the next VO restart attempt, reducing the thermal stress to the components. If the FLT pin is not used, the pin can be left floating but can not be connected to REF pin, since the line OVP will be falsely triggered.

The thermal issue in the heavy output load condition is the main design consideration for OTP, and the heavy load operating mode, AAM, allows the controller to stay in the run state continuously, so the 50-μs delay allows VFLT to trigger OTP. Based on the practical BUR-pin setting, 50% to 60% load is operated in AAM. The 50-μA current source is disabled in the burst off time of the light load modes such as ABM, LPM, SBP1, and SBP2, in order to save standby power. However, when the run state becomes shorter than the 50-μs in these modes but the current source is disabled in the wait state, the OTP will not be able to trigger because there is not enough time to detect the fault. Therefore, if certain design considerations still require the OTP to be armed in light load modes, a second OTP configuration can be considered by reusing the 4.5-V threshold of input OVP. As shown in Figure 7-40, the upper NTC resistor and the lower resistor form a resistor divider from the REF pin to the FLT pin. The 750-μs delay is independent to the wait state condition of controller, so the OTP fault can still be triggered in the light load mode.

GUID-51072C2B-53A4-4393-9C02-CC9D7C3084E1-low.gif Figure 7-40 Two Connections to Implement OTP on the FLT Pin
GUID-D7D94D32-B18D-4561-8BD9-B71721859D4C-low.gif Figure 7-41 OTP Timing Diagram for a NTC between the FLT Pin and AGND Pin