SLUS458H Data sheet

SLUS458H July 2000 – November 2022 UCC28C40 , UCC28C41 , UCC28C42 , UCC28C43 , UCC28C44 , UCC28C45 , UCC38C40 , UCC38C41 , UCC38C42 , UCC38C43 , UCC38C44 , UCC38C45

PRODUCTION DATA

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)

D|8
DGK|8

Thermal pad, mechanical data (Package|Pins)

DGK|8
- QFND519

Orderable Information

7.5 Electrical Characteristics

V_VDD = 15 V ⁽¹⁾, R_RT = 10 kΩ, C_CT = 3.3 nF, C_VDD = 0.1 µF and no load on the outputs, T_J = –40°C to 125 °C for the UCC28C4x and T_J = 0°C to 85 °C for the UCC38C4x (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
REFERENCE
V_VREF	VREF voltage, initial accuracy	T_J = 25°C, I_OUT = 1 mA	4.9	5	5.1	V
	Line regulation	V_VDD = 12 V to 18 V		0.2	20	mV
	Load regulation	1 mA to 20 mA		3	25	mV
	Temperature stability	See ⁽²⁾		0.2	0.4	mV/°C
	Total output variation	See ⁽²⁾	4.82		5.18	V
	VREF noise voltage	10 Hz to 10 kHz, T_J = 25°C, see ⁽²⁾		50		µV
	Long term stability	1000 hours, T_J = 125°C, see ⁽²⁾		5	25	mV
I_VREF	Output short circuit (source current)		30	45	55	mA
OSCILLATOR
f_OSC	Initial accuracy	T_J = 25°C, see ⁽³⁾	50.5	53	55	kHz
	Voltage stability	12 V ≤ V_VDD ≤ 18 V		0.2%	1%
	Temperature stability	T_J(MIN) to T_J(MAX), see ⁽²⁾		1%	2.5%
	Amplitude	RT/CT pin peak-to-peak voltage		1.9		V
	Discharge current	T_J = 25°C, V_RT/CT = 2 V, see ⁽⁴⁾	7.7	8.4	9	mA
	Discharge current	V_RT/CT = 2 V, see ⁽⁴⁾	7.2	8.4	9.5	mA
ERROR AMPLIFIER
V_FB	Feedback input voltage, initial accuracy	V_COMP = 2.5 V, T_J = 25°C	2.475	2.5	2.525	V
	Feedback input voltage, total variation	V_COMP = 2.5 V	2.45	2.5	2.55	V
I_FB	Input bias current (source current)	V_FB = 5 V		0.1	2	µA
A_VOL	Open-loop voltage gain	2 V ≤ V_OUT ≤ 4 V	65	90		dB
	Unity gain bandwidth	See ⁽²⁾	1	1.5		MHz
PSRR	Power supply rejection ratio	12 V ≤ V_VDD ≤ 18 V	60			dB
	Output sink current	V_FB = 2.7 V, V_COMP = 1.1 V	2	14		mA
	Output source current	V_FB = 2.3 V, V_COMP = 5 V	0.5	1		mA
VOH	High-level COMP voltage	V_FB = 2.7 V, R_COMP = 15 kΩ COMP to GND	V_REF - 0.2			V
VOL	Low-level COMP voltage	V_FB = 2.7 V, R_COMP = 15 kΩ COMP to VREF		0.1	1.1	V
CURRENT SENSE
A_CS	Gain	See ⁽⁵⁾⁽⁶⁾	2.85	3	3.15	V/V
V_CS	Maximum input signal	V_FB < 2.4 V	0.9	1	1.1	V
PSRR	Power supply rejection ratio	V_VDD = 12 V to 18 V⁽²⁾⁽⁵⁾		70		dB
I_CS	Input bias current (source current)			0.1	2	µA
t_D	CS to output delay			35	70	ns
	COMP to CS offset	V_CS = 0 V		1.15		V
OUTPUT
V_OUT(low)	R_DS(on) pulldown	I_SINK = 200 mA		5.5	15	Ω
V_OUT(high)	R_DS(on) pullup	I_SOURCE = 200 mA		10	25	Ω
t_RISE	Rise tIme	T_J = 25°C, C_OUT = 1 nF		25	50	ns
t_FALL	Fall tIme	T_J = 25°C, C_OUT = 1 nF		20	40	ns
UNDERVOLTAGE LOCKOUT
VDD_ON	Start threshold	UCCx8C42, UCCx8C44	13.5	14.5	15.5	V
		UCCx8C43, UCCx8C45	7.8	8.4	9
		UCCx8C40, UCCx8C41	6.5	7	7.5
VDD_OFF	Minimum operating voltage	UCCx8C42, UCCx8C44	8	9	10	V
		UCCx8C43, UCCx8C45	7	7.6	8.2
		UCCx8C40, UCCx8C41	6.1	6.6	7.1
PWM
D_MAX	Maximum duty cycle	UCCx8C42, UCCx8C43, UCCx8C40, V_FB < 2.4 V	94%	96%
D_MAX	Maximum duty cycle	UCCx8C44, UCCx8C45, UCCx8C41, V_FB < 2.4 V	47%	48%
D_MIN	Minimum duty cycle	V_FB > 2.6 V			0%
CURRENT SUPPLY
I_START-UP	Start-up current	V_VDD = VDD_ON – 0.5 V		50	100	µA
I_VDD	Operating supply current	V_FB = V_CS = 0 V		2.3	3	mA

(1) Adjust V_VDD above the start threshold before setting at and 15.5 V.

(2) Specified by design. Not production tested.

(3) Output frequencies of the UCCx8C41, UCCx8C44, and the UCCx8C45 are half the oscillator frequency.

(4) Oscillator discharge current is measured with R_RT = 10 kΩ to VREF.

(5) Parameter measured at trip point of latch with V_FB = 0 V.

(6) Gain is defined as A_CS = ΔV_COMP / ΔV_CS , 0 V ≤ V_CS ≤ 900 mV