Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The UCC39002 is an advanced, high-performance load-share controller that provides all the necessary functions to parallel multiple independent power supplies or DC-to-DC modules. This load-share circuit is based upon the automatic master or slave architecture used in the UC3902 and the UC3907 load-share controllers providing better than 1% current-share error between the modules at full load.
In order to properly configure and design with the UCC39002 it necessary to gather requirements for the following system level performance metrics.
1. Required system level stability to include phase margin (φm), gain margin (gm), and bandwidth (fbw). Typical values are φm = 45 °, gm = 10 dB, and fbw= fs/10 where fs is the switching frequency.
2. Required current sharing accuracy. Typically this is 1 %.
The following is a practical step-by-step design procedure on how to use the UCC39002 to parallel power modules for load sharing.
Selection of the shunt resistor is limited by its voltage drop at maximum module output current. This voltage drop should be much less than the voltage adjustment range of the module shown in Equation 3:
Other limitations for the sense resistor are the desired minimum power dissipation and available component ratings.
The gain of the current sense amplifier is configured by the compensation components between Pin 1, CS−, and Pin 8, CSO, of the load share device. The voltage at the CSO pin is limited by the saturation voltage of the internal current sense amplifier and must be at least two volts less than VDD in Equation 4:
The maximum current sense amplifier gain is equal to Equation 5:
Referring to Figure 6, the gain is equal to R16/R15 and a high-frequency pole, configured with C13, is used for noise filtering. This impedance is mirrored at the CS+ pin of the differential amplifier as shown.
The current sense amplifier output voltage, VCSO, serves as the input to the unity gain LS bus driver. The module with the highest output voltage forward biases the internal diode at the output of the LS bus driver and determine the voltage on the load share bus, VLS. The other modules act as slaves and represent a load on the IVDD of the module due to the internal 100-kΩ resistor at the LS pin. This increase in supply current for the master module is equal to N(VLS/100 kΩ).
The Sense+ terminal of the module is connected to the ADJ pin of the load-share controller. By placing a resistor between this ADJ pin and the load, an artificial Sense+ voltage is created from the voltage drop across RADJUST due to the current sunk by the internal NPN transistor. The voltage at the ADJ pin must be maintained at approximately 1 V above the voltage at the EAO pin. This is necessary in order to keep the transistor at the output of the internal adjust amplifier from saturating. To fulfill this requirement, RADJUST is first calculated using Equation 6:
Also needed for consideration is the actual adjust pin current. The maximum sink current for the ADJ pin, IADJmax, is 6 mA as determined by the internal 500-Ω emitter resistor and 3-V clamp. The value of adjust resistor, RADJUST, is based upon the maximum adjustment range of the module, ΔVADJmax. This adjust resistor is determined using Equation 7:
By selecting a resistor that meets both of these minimum requirements, the ADJ pin will be at least 1 V greater than the EAO voltage and the adjust pin sink current will not exceed its 6 mA maximum.
The total load-share loop unity-gain crossover frequency, fCO, must be set at least one decade below the measured crossover frequency of the paralleled modules previously measured, fCO(module). (See Figure 8) Compensation of the transconductance error amplifier is accomplished by placing the compensation resistor, REAO, and capacitor, CEAO, between EAO and GND. The values of these components is determined using Equation 8 and Equation 13.
Once the CEAO capacitor is determined, REAO is selected to achieve the desired loop response, using Equation 13: