SLUS495I September   2001  – May 2016 UCC29002 , UCC39002

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Differential Current Sense Amplifier (CS+, CS−, CSO)
      2. 7.3.2  Load Share Bus Driver Amplifier (CSO)
      3. 7.3.3  Load Share Bus Receiver Amplifier (LS)
      4. 7.3.4  Error Amplifier (EAO)
      5. 7.3.5  Adjust Amplifier Output (ADJ)
      6. 7.3.6  Enable Function (CS+, CS−)
      7. 7.3.7  Fault Protection
      8. 7.3.8  Start-Up and Adjust Logic
      9. 7.3.9  Bias and Bias OK Circuit (VDD)
      10. 7.3.10 Paralleling the Power Modules
      11. 7.3.11 Measuring the Loop of the Modules
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fault
      2. 7.4.2 Start-Up
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 The Shunt Resistor
        2. 8.2.2.2 The CSA Gain
        3. 8.2.2.3 Determining RADJUST
        4. 8.2.2.4 Error Amplifier Compensation
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The UCC39002 is an advanced, high-performance load-share controller that provides all the necessary functions to parallel multiple independent power supplies or DC-to-DC modules. This load-share circuit is based upon the automatic master or slave architecture used in the UC3902 and the UC3907 load-share controllers providing better than 1% current-share error between the modules at full load.

8.2 Typical Application

UCC29002 UCC29002-1 UCC39002 typical_high_side_current_sensing_app_slus495.gif Figure 9. Typical High-Side Current-Sensing Application

8.2.1 Design Requirements

In order to properly configure and design with the UCC39002 it necessary to gather requirements for the following system level performance metrics.

1. Required system level stability to include phase margin (φm), gain margin (gm), and bandwidth (fbw). Typical values are φm = 45 °, gm = 10 dB, and fbw= fs/10 where fs is the switching frequency.

2. Required current sharing accuracy. Typically this is 1 %.

8.2.2 Detailed Design Procedure

The following is a practical step-by-step design procedure on how to use the UCC39002 to parallel power modules for load sharing.

8.2.2.1 The Shunt Resistor

Selection of the shunt resistor is limited by its voltage drop at maximum module output current. This voltage drop should be much less than the voltage adjustment range of the module shown in Equation 3:

Equation 3. UCC29002 UCC29002-1 UCC39002 Eq03_delta_slus495.gif

Other limitations for the sense resistor are the desired minimum power dissipation and available component ratings.

8.2.2.2 The CSA Gain

The gain of the current sense amplifier is configured by the compensation components between Pin 1, CS−, and Pin 8, CSO, of the load share device. The voltage at the CSO pin is limited by the saturation voltage of the internal current sense amplifier and must be at least two volts less than VDD in Equation 4:

Equation 4. UCC29002 UCC29002-1 UCC39002 Eq04_vcso_slus495.gif

The maximum current sense amplifier gain is equal to Equation 5:

Equation 5. UCC29002 UCC29002-1 UCC39002 Eq05_ACSA_slus495.gif

Referring to Figure 6, the gain is equal to R16/R15 and a high-frequency pole, configured with C13, is used for noise filtering. This impedance is mirrored at the CS+ pin of the differential amplifier as shown.

The current sense amplifier output voltage, VCSO, serves as the input to the unity gain LS bus driver. The module with the highest output voltage forward biases the internal diode at the output of the LS bus driver and determine the voltage on the load share bus, VLS. The other modules act as slaves and represent a load on the IVDD of the module due to the internal 100-kΩ resistor at the LS pin. This increase in supply current for the master module is equal to N(VLS/100 kΩ).

8.2.2.3 Determining RADJUST

The Sense+ terminal of the module is connected to the ADJ pin of the load-share controller. By placing a resistor between this ADJ pin and the load, an artificial Sense+ voltage is created from the voltage drop across RADJUST due to the current sunk by the internal NPN transistor. The voltage at the ADJ pin must be maintained at approximately 1 V above the voltage at the EAO pin. This is necessary in order to keep the transistor at the output of the internal adjust amplifier from saturating. To fulfill this requirement, RADJUST is first calculated using Equation 6:

Equation 6. UCC29002 UCC29002-1 UCC39002 Eq06_Radjust_slus495.gif

where

  • RSHUNT is the current sense resistor,
  • and RSENSE is the internal resistance between VOUT+ and SENSE+ within the module.

Also needed for consideration is the actual adjust pin current. The maximum sink current for the ADJ pin, IADJmax, is 6 mA as determined by the internal 500-Ω emitter resistor and 3-V clamp. The value of adjust resistor, RADJUST, is based upon the maximum adjustment range of the module, ΔVADJmax. This adjust resistor is determined using Equation 7:

Equation 7. UCC29002 UCC29002-1 UCC39002 Eq07_RADJUST_slus495.gif

By selecting a resistor that meets both of these minimum requirements, the ADJ pin will be at least 1 V greater than the EAO voltage and the adjust pin sink current will not exceed its 6 mA maximum.

8.2.2.4 Error Amplifier Compensation

The total load-share loop unity-gain crossover frequency, fCO, must be set at least one decade below the measured crossover frequency of the paralleled modules previously measured, fCO(module). (See Figure 8) Compensation of the transconductance error amplifier is accomplished by placing the compensation resistor, REAO, and capacitor, CEAO, between EAO and GND. The values of these components is determined using Equation 8 and Equation 13.

Equation 8. UCC29002 UCC29002-1 UCC39002 Eq08_ILmax_slus495.gif

where

  • gM is the transconductance of the error amplifier, typically 14 mS,
  • fCO is equal to the desired crossover frequency in Hz of the load share loop, typically fCO (module)/10,
  • ACSA is the CSA gain,
  • AV is the voltage gain,
  • AADJ is the gain associated with the adjust amplifier,
  • |APWR(fCO)| is the measured gain of the power module at the desired load share crossover frequency, fCO, converted to V/V from dB
Equation 9. UCC29002 UCC29002-1 UCC39002 Eq09_ACSA_slus495.gif
Equation 10. UCC29002 UCC29002-1 UCC39002 Eq10_AV_slus495.gif
Equation 11. UCC29002 UCC29002-1 UCC39002 Eq11_AADJ_slus495.gif
Equation 12. UCC29002 UCC29002-1 UCC39002 Eq12_apwr_slus495.gif

where

  • GMODULE(fco) is the measured value of the gain from Figure 8, at the desired crossover frequency.

Once the CEAO capacitor is determined, REAO is selected to achieve the desired loop response, using Equation 13:

Equation 13. UCC29002 UCC29002-1 UCC39002 Eq13_REAO_slus495.gif

8.2.3 Application Curve

UCC29002 UCC29002-1 UCC39002 power_module_bode_plot_slus495.gif Figure 10. Power Module Bode Plot