SLUS495I September   2001  – May 2016 UCC29002 , UCC39002

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Differential Current Sense Amplifier (CS+, CS−, CSO)
      2. 7.3.2  Load Share Bus Driver Amplifier (CSO)
      3. 7.3.3  Load Share Bus Receiver Amplifier (LS)
      4. 7.3.4  Error Amplifier (EAO)
      5. 7.3.5  Adjust Amplifier Output (ADJ)
      6. 7.3.6  Enable Function (CS+, CS−)
      7. 7.3.7  Fault Protection
      8. 7.3.8  Start-Up and Adjust Logic
      9. 7.3.9  Bias and Bias OK Circuit (VDD)
      10. 7.3.10 Paralleling the Power Modules
      11. 7.3.11 Measuring the Loop of the Modules
    4. 7.4 Device Functional Modes
      1. 7.4.1 Fault
      2. 7.4.2 Start-Up
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 The Shunt Resistor
        2. 8.2.2.2 The CSA Gain
        3. 8.2.2.3 Determining RADJUST
        4. 8.2.2.4 Error Amplifier Compensation
      3. 8.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VDD Supply voltage, current limited −0.3 15 V
VDD Supply voltage, voltage source −0.3 13.5 V
VCS+, VCS− Input voltage, current sense amplifier –0.3 VDD + 0.3 V
VCSO Current sense amplifier output voltage −0.3 VDD V
VLS Load share bus voltage −0.3 VDD V
Supply current (IDD + IZENER) 10 mA
VADJ Adjust pin input voltage VEAO +1 V < VADJ ≤ VDD
IADJ Adjust pin sink current 6 mA
TJ Operating junction temperature range −55 150 °C
Tstg Storage temperature −65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to GND. Currents are positive into, negative out of the specified terminal.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VDD Supply voltage, voltage source 4.575 13.5 V
VCSO Current sense amplifier output voltage 0 11.8 V
VLS Load share bus voltage 0 VDD – 1.7 V
IADJ Adjust pin sink current 4.55 mA

6.4 Thermal Information

THERMAL METRIC(1) UCC2900x/UCC39002 UNIT
D (SOIC) DGK (VSSOP) P (PDIP)
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 111.9 168.0 54.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 58.6 61.9 43.9 °C/W
RθJB Junction-to-board thermal resistance 52.6 88.8 31.2 °C/W
ψJT Junction-to-top characterization parameter 12.9 7.3 21.6 °C/W
ψJB Junction-to-board characterization parameter 52.0 87.2 31.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

VDD = 12 V, 0°C < 70°C for the UCC39002, –40°C < TA < 105°C for the UCC29002 and UCC29002-1, TA = TJ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
GENERAL
Supply current LS with no load, ADJ = 5 V 2.5 3.5 mA
VDD clamp voltage IDD = 6 mA 13.5 14.25 15 V
UNDERVOLTAGE LOCKOUT
Start-up voltage(1) 4.175 4.375 4.575 V
Hysteresis 0.2 0.375 0.55
CURRENT SENSE AMPLIFIER
VIO Input offset voltage TA = 25 C, VIC = 0.5 V or 11.5 V, VCSO = 5 V −100 100 µV
Overtemperature variation ±10 µV/ C
AV Gain 75 90 dB
CMRR Common-mode rejection ratio 75 90 dB
IBIAS Input bias current (CS+, CS−) −0.6 0.6 µA
VOH High-level output voltage (CSO) 0.1 V ≤ ([CS+] − [CS−]) ≤ 0.4 V, IOUT_CSO = 0 mA 10.7 11 11.8 V
VOL Low-level output voltage (CSO) −0.4 V ≤ ([CS+] − [CS−]) ≤ 0.1 V, IOUT_CSO = 0 mA 0 0.1 0.15 V
IOH High-level output current (CSO) VCSO = 10 V −1 −1.5 mA
IOL Low-level output current (CSO) VCSO = 1 V 1 1.5 mA
GBW Gain bandwidth product(2) 2 MHz
LOAD SHARE DRIVER (LS)
VRANGE Input voltage range 0 10 V
VOUT Output voltage VCSO = 1 V 0.995 1 1.005 V
VCSO = 10 V 0.995 10 1.005
VOL Low-level output voltage VCSO = 0 V, IOUT_LS = 0 mA 0 0.1 0.15 V
VOH High-level output voltage(2) VDD − 1.7 V
IOUT Output current 0.5 V ≤ VLS ≤ 10 V −1 −1.5 V
ISC Short-circuit current VLS = 0 V, VCSO = 10 V −10 −20 mA
VSHTDN Driver shutdown threshold VCS− − VCS+ 0.3 0.5 0.7 V
LOAD SHARE BUS PROTECTION
IADJ Adjust amplifier current VCSO = 2 V, VEAO = 2 V, VLS = VDD, VADJ = 5 V 0 5 10 µA
VCSO = 2 V, VEAO = 2 V, VLS = 0 V, VADJ = 5 V 0 5 10
ERROR AMPLIFIER
VOH High-level output voltage IOUT_EAO = 0 mA 3.5 3.65 3.8 V
gM Transconductance IEAO = ± 50 µA 14 mS
IOH High-level output current VLS − VCSO = 0.4 V, REAO = 2.2 kΩ 0.7 0.85 1 mA
ADJ BUFFER
VIO Input offset voltage(2) VADJ = 1.5 V, VEAO = 0 V −60 mV
ISINK Sink current VADJ = 5.0 V, VEAO = 0 V 0 5 10 µA
ISINK Sink current TA = 25°C VADJ = 5.0 V,
VEAO = 2.0 V,
LS = floating
3.6 3.95 4.3 mA
0°C ≤ TA ≤ 70°C 3.45 3.95 4.45
−40°C ≤ TA ≤ 105°C 3.35 3.95 4.55
(1) Enables the load share bus at start-up.
(2) Ensured by design. Not production tested.

6.6 Typical Characteristics

UCC29002 UCC29002-1 UCC39002 Load_Share_Error_Results_SLUS495.gif Figure 1. Resultant Load Current Sharing Accuracy, as Measured Across Shunts from the Output of Each Module