SNLS571B March   2018  – September 2018 DS90UB936-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Typical Application Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  DC Electrical Characteristics
    6. 6.6  AC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics CSI-2
    8. 6.8  Recommended Timing for the Serial Control Bus
    9. 6.9  Timing Diagrams
    10. 6.10 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
      1. 7.1.1 Functional Description
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
      1. 7.4.1  CSI-2 Mode
      2. 7.4.2  RAW Mode
      3. 7.4.3  RX MODE Pin
      4. 7.4.4  REFCLK
      5. 7.4.5  Crystal Recommendations
      6. 7.4.6  Receiver Port Control
        1. 7.4.6.1 Video Stream Forwarding
      7. 7.4.7  LOCK and PASS Status
      8. 7.4.8  Input Jitter Tolerance
      9. 7.4.9  Adaptive Equalizer
        1. 7.4.9.1 Adaptive Equalizer Algorithm
        2. 7.4.9.2 AEQ Settings
          1. 7.4.9.2.1 AEQ Start-Up and Initialization
          2. 7.4.9.2.2 AEQ Range
          3. 7.4.9.2.3 AEQ Timing
          4. 7.4.9.2.4 AEQ Threshold
      10. 7.4.10 Channel Monitor Loop-Through Output Driver (CMLOUT)
        1. 7.4.10.1 Code Example for CMLOUT FPD-Link III RX Port 0:
      11. 7.4.11 RX Port Status
        1. 7.4.11.1 RX Parity Status
        2. 7.4.11.2 FPD-Link Decoder Status
        3. 7.4.11.3 RX Port Input Signal Detection
        4. 7.4.11.4 Line Counter
        5. 7.4.11.5 Line Length
      12. 7.4.12 Sensor Status
      13. 7.4.13 GPIO Support
        1. 7.4.13.1 GPIO Input Control and Status
        2. 7.4.13.2 GPIO Output Pin Control
        3. 7.4.13.3 Forward Channel GPIO
        4. 7.4.13.4 Back Channel GPIO
        5. 7.4.13.5 Other GPIO Pin Controls
      14. 7.4.14 Line Valid and Frame Valid Indicators
      15. 7.4.15 CSI-2 Protocol Layer
      16. 7.4.16 CSI-2 Short Packet
      17. 7.4.17 CSI-2 Long Packet
      18. 7.4.18 CSI-2 Data Type Identifier
      19. 7.4.19 Virtual Channel and Context
      20. 7.4.20 CSI-2 Input Mode Virtual Channel Mapping
        1. 7.4.20.1 Example 1
        2. 7.4.20.2 Example 2:
      21. 7.4.21 CSI-2 Transmitter Frequency
      22. 7.4.22 CSI-2 Replicate Mode
      23. 7.4.23 CSI-2 Transmitter Output Control
      24. 7.4.24 CSI-2 Transmitter Status
      25. 7.4.25 Video Buffers
      26. 7.4.26 CSI-2 Line Count and Line Length
      27. 7.4.27 FrameSync Operation
        1. 7.4.27.1 External FrameSync Control
        2. 7.4.27.2 Internally Generated FrameSync
          1. 7.4.27.2.1 Code Example for Internally Generated FrameSync
      28. 7.4.28 CSI-2 Forwarding
        1. 7.4.28.1 Enabling and Disabling the CSI-2 Transmitter
        2. 7.4.28.2 Best-Effort Round Robin CSI-2 Forwarding
        3. 7.4.28.3 Synchronized Forwarding
        4. 7.4.28.4 Basic Synchronized Forwarding
          1. 7.4.28.4.1 Code Example for Basic Synchronized Forwarding
        5. 7.4.28.5 Line-Interleave Forwarding
          1. 7.4.28.5.1 Code Example for Line-Interleave Forwarding
        6. 7.4.28.6 Line-Concatenated Forwarding
          1. 7.4.28.6.1 Code Example for Line-Concatenate Forwarding
    5. 7.5 Programming
      1. 7.5.1  Serial Control Bus and Bidirectional Control Channel
        1. 7.5.1.1 Bidirectional Control
        2. 7.5.1.2 Device Address
        3. 7.5.1.3 Basic I2C Serial Bus Operation
      2. 7.5.2  I2C Slave Operation
      3. 7.5.3  Remote Slave Operation
        1. 7.5.3.1 Remote I2C Slaves Data Throughput
      4. 7.5.4  Remote Slave Addressing
      5. 7.5.5  Broadcast Write to Remote Slave Devices
        1. 7.5.5.1 Code Example for Broadcast Write
      6. 7.5.6  I2C Master Proxy
      7. 7.5.7  I2C Master Proxy Timing
        1. 7.5.7.1 Code Example for Configuring Fast Mode Plus I2C Operation
      8. 7.5.8  Interrupt Support
        1. 7.5.8.1 Code Example to Enable Interrupts
        2. 7.5.8.2 FPD-Link III Receive Port Interrupts
          1. 7.5.8.2.1 Interrupts on Forward Channel GPIO
          2. 7.5.8.2.2 Interrupts on Change in Sensor Status
        3. 7.5.8.3 Code Example to Readback Interrupts
        4. 7.5.8.4 CSI-2 Transmit Port Interrupts
      9. 7.5.9  Error Handling
        1. 7.5.9.1 Receive Frame Threshold
        2. 7.5.9.2 Port PASS Control
      10. 7.5.10 Timestamp – Video Skew Detection
      11. 7.5.11 Pattern Generation
        1. 7.5.11.1 Reference Color Bar Pattern
        2. 7.5.11.2 Fixed Color Patterns
        3. 7.5.11.3 Packet Generator Programming
          1. 7.5.11.3.1 Determining Color Bar Size
        4. 7.5.11.4 Code Example for Pattern Generator
      12. 7.5.12 FPD-Link BIST Mode
        1. 7.5.12.1 BIST Operation Through BISTEN Pin
        2. 7.5.12.2 BIST Operation Through Register Control
    6. 7.6 Register Maps
      1. 7.6.1   I2C Device ID Register
        1. Table 19. I2C Device ID (Address 0x00)
      2. 7.6.2   Reset Register
        1. Table 20. Reset (Address 0x01)
      3. 7.6.3   General Configuration Register
        1. Table 21. General Configuration (Address 0x02)
      4. 7.6.4   Revision/Mask ID Register
        1. Table 22. Revision/Mask ID (Address 0x03)
      5. 7.6.5   DEVICE_STS Register
        1. Table 23. DEVICE_STS (Address 0x04)
      6. 7.6.6   PAR_ERR_THOLD_HI Register
        1. Table 24. PAR_ERR_THOLD_HI (Address 0x05)
      7. 7.6.7   PAR_ERR_THOLD_LO Register
        1. Table 25. PAR_ERR_THOLD_LO (Address 0x06)
      8. 7.6.8   BCC Watchdog Control Register
        1. Table 26. BCC Watchdog Control (Address 0x07)
      9. 7.6.9   I2C Control 1 Register
        1. Table 27. I2C Control 1 (Address 0x08)
      10. 7.6.10  I2C Control 2 Register
        1. Table 28. I2C Control 2 (Address 0x09)
      11. 7.6.11  SCL High Time Register
        1. Table 29. SCL High Time (Address 0x0A)
      12. 7.6.12  SCL Low Time Register
        1. Table 30. SCL Low Time (Address 0x0B)
      13. 7.6.13  RX_PORT_CTL Register
        1. Table 31. RX_PORT_CTL (Address 0x0C)
      14. 7.6.14  IO_CTL Register
        1. Table 32. IO_CTL (Address 0x0D)
      15. 7.6.15  GPIO_PIN_STS Register
        1. Table 33. GPIO_PIN_STS (Address 0x0E)
      16. 7.6.16  GPIO_INPUT_CTL Register
        1. Table 34. GPIO_INPUT_CTL (Address 0x0F)
      17. 7.6.17  GPIO0_PIN_CTL Register
        1. Table 35. GPIO0_PIN_CTL (Address 0x10)
      18. 7.6.18  GPIO1_PIN_CTL Register
        1. Table 36. GPIO1_PIN_CTL (Address 0x11)
      19. 7.6.19  GPIO2_PIN_CTL Register
        1. Table 37. GPIO2_PIN_CTL (Address 0x12)
      20. 7.6.20  GPIO3_PIN_CTL Register
        1. Table 38. GPIO3_PIN_CTL (Address 0x13)
      21. 7.6.21  GPIO4_PIN_CTL Register
        1. Table 39. GPIO4_PIN_CTL (Address 0x14)
      22. 7.6.22  GPIO5_PIN_CTL Register
        1. Table 40. GPIO5_PIN_CTL (Address 0x15)
      23. 7.6.23  GPIO6_PIN_CTL Register
        1. Table 41. GPIO6_PIN_CTL (Address 0x16)
      24. 7.6.24  RESERVED Register
        1. Table 42. RESERVED (Address 0x17)
      25. 7.6.25  FS_CTL Register
        1. Table 43. FS_CTL (Address 0x18)
      26. 7.6.26  FS_HIGH_TIME_1 Register
        1. Table 44. FS_HIGH_TIME_1 (Address 0x19)
      27. 7.6.27  FS_HIGH_TIME_0 Register
        1. Table 45. FS_HIGH_TIME_0 (Address 0x1A)
      28. 7.6.28  FS_LOW_TIME_1 Register
        1. Table 46. FS_LOW_TIME_1 (Address 0x1B)
      29. 7.6.29  FS_LOW_TIME_0 Register
        1. Table 47. FS_LOW_TIME_0 (Address 0x1C)
      30. 7.6.30  MAX_FRM_HI Register
        1. Table 48. MAX_FRM_HI (Address 0x1D)
      31. 7.6.31  MAX_FRM_LO Register
        1. Table 49. MAX_FRM_LO (Address 0x1E)
      32. 7.6.32  CSI_PLL_CTL Register
        1. Table 50. CSI_PLL_CTL (Address 0x1F)
      33. 7.6.33  FWD_CTL1 Register
        1. Table 51. FWD_CTL1 (Address 0x20)
      34. 7.6.34  FWD_CTL2 Register
        1. Table 52. FWD_CTL2 (Address 0x21)
      35. 7.6.35  FWD_STS Register
        1. Table 53. FWD_STS (Address 0x22)
      36. 7.6.36  INTERRUPT_CTL Register
        1. Table 54. INTERRUPT_CTL (Address 0x23)
      37. 7.6.37  INTERRUPT_STS Register
        1. Table 55. INTERRUPT_STS (Address 0x24)
      38. 7.6.38  TS_CONFIG Register
        1. Table 56. TS_CONFIG (Address 0x25)
      39. 7.6.39  TS_CONTROL Register
        1. Table 57. TS_CONTROL (Address 0x26)
      40. 7.6.40  TS_LINE_HI Register
        1. Table 58. TS_LINE_HI (Address 0x27)
      41. 7.6.41  TS_LINE_LO Register
        1. Table 59. TS_LINE_LO (Address 0x28)
      42. 7.6.42  TS_STATUS Register
        1. Table 60. TS_STATUS (Address 0x29)
      43. 7.6.43  TIMESTAMP_P0_HI Register
        1. Table 61. TIMESTAMP_P0_HI (Address 0x2A)
      44. 7.6.44  TIMESTAMP_P0_LO Register
        1. Table 62. TIMESTAMP_P0_LO (Address 0x2B)
      45. 7.6.45  TIMESTAMP_P1_HI Register
        1. Table 63. TIMESTAMP_P1_HI (Address 0x2C)
      46. 7.6.46  TIMESTAMP_P1_LO Register
        1. Table 64. TIMESTAMP_P1_LO (Address 0x2D)
      47. 7.6.47  RESERVED Register
        1. Table 65. RESERVED (Address 0x2E – 0x32)
      48. 7.6.48  CSI_CTL Register
        1. Table 66. CSI_CTL (Address 0x33)
      49. 7.6.49  CSI_CTL2 Register
        1. Table 67. CSI_CTL2 (Address 0x34)
      50. 7.6.50  CSI_STS Register
        1. Table 68. CSI_STS (Address 0x35)
      51. 7.6.51  CSI_TX_ICR Register
        1. Table 69. CSI_TX_ICR (Address 0x36)
      52. 7.6.52  CSI_TX_ISR Register
        1. Table 70. CSI_TX_ISR (Address 0x37)
      53. 7.6.53  CSI_TEST_CTL Register
        1. Table 71. CSI_TEST_CTL (Address 0x38)
      54. 7.6.54  CSI_TEST_PATT_HI Register
        1. Table 72. CSI_TEST_PATT_HI (Address 0x39)
      55. 7.6.55  CSI_TEST_PATT_LO Register
        1. Table 73. CSI_TEST_PATT_LO (Address 0x3A)
      56. 7.6.56  RESERVED Register
        1. Table 74. RESERVED (Address 0x3B)
      57. 7.6.57  RESERVED Register
        1. Table 75. RESERVED (Address 0x3C)
      58. 7.6.58  RESERVED Register
        1. Table 76. RESERVED (Address 0x3D)
      59. 7.6.59  RESERVED Register
        1. Table 77. RESERVED (Address 0x3E)
      60. 7.6.60  RESERVED Register
        1. Table 78. RESERVED (Address 0x3F)
      61. 7.6.61  RESERVED Register
        1. Table 79. RESERVED (Address 0x40)
      62. 7.6.62  SFILTER_CFG Register
        1. Table 80. SFILTER_CFG (Address 0x41)
      63. 7.6.63  AEQ_CTL1 Register
        1. Table 81. AEQ_CTL1 (Address 0x42)
      64. 7.6.64  AEQ_ERR_THOLD Register
        1. Table 82. AEQ_ERR_THOLD (Address 0x43)
      65. 7.6.65  RESERVED Register
        1. Table 83. RESERVED (Address 0x44 – 0x49)
      66. 7.6.66  FPD3_CAP Register
        1. Table 84. FPD3_CAP (Address 0x4A)
      67. 7.6.67  RAW_EMBED_DTYPE Register
        1. Table 85. RAW_EMBED_DTYPE (Address 0x4B)
      68. 7.6.68  FPD3_PORT_SEL Register
        1. Table 86. FPD3_PORT_SEL (Address 0x4C)
      69. 7.6.69  RX_PORT_STS1 Register
        1. Table 87. RX_PORT_STS1 (Address 0x4D)
      70. 7.6.70  RX_PORT_STS2 Register
        1. Table 88. RX_PORT_STS2 (Address 0x4E)
      71. 7.6.71  RX_FREQ_HIGH Register
        1. Table 89. RX_FREQ_HIGH (Address 0x4F)
      72. 7.6.72  RX_FREQ_LOW Register
        1. Table 90. RX_FREQ_LOW (Address 0x50)
      73. 7.6.73  SENSOR_STS_0 Register
        1. Table 91. SENSOR_STS_0 (Address 0x51)
      74. 7.6.74  SENSOR_STS_1 Register
        1. Table 92. SENSOR_STS_1 (Address 0x52)
      75. 7.6.75  SENSOR_STS_2 Register
        1. Table 93. SENSOR_STS_2 (Address 0x53)
      76. 7.6.76  SENSOR_STS_3 Register
        1. Table 94. SENSOR_STS_3 (Address 0x54)
      77. 7.6.77  RX_PAR_ERR_HI Register
        1. Table 95. RX_PAR_ERR_HI (Address 0x55)
      78. 7.6.78  RX_PAR_ERR_LO Register
        1. Table 96. RX_PAR_ERR_LO (Address 0x56)
      79. 7.6.79  BIST_ERR_COUNT Register
        1. Table 97. BIST_ERR_COUNT (Address 0x57)
      80. 7.6.80  BCC_CONFIG Register
        1. Table 98. BCC_CONFIG (Address 0x58)
      81. 7.6.81  DATAPATH_CTL1 Register
        1. Table 99. DATAPATH_CTL1 (Address 0x59)
      82. 7.6.82  DATAPATH_CTL2 Register
        1. Table 100. DATAPATH_CTL2 (Address 0x5A)
      83. 7.6.83  SER_ID Register
        1. Table 101. SER_ID (Address 0x5B)
      84. 7.6.84  SER_ALIAS_ID Register
        1. Table 102. SER_ALIAS_ID (Address 0x5C)
      85. 7.6.85  SlaveID[0] Register
        1. Table 103. SlaveID[0] (Address 0x5D)
      86. 7.6.86  SlaveID[1] Register
        1. Table 104. SlaveID[1] (Address 0x5E)
      87. 7.6.87  SlaveID[2] Register
        1. Table 105. SlaveID[2] (Address 0x5F)
      88. 7.6.88  SlaveID[3] Register
        1. Table 106. SlaveID[3] (Address 0x60)
      89. 7.6.89  SlaveID[4] Register
        1. Table 107. SlaveID[4] (Address 0x61)
      90. 7.6.90  SlaveID[5] Register
        1. Table 108. SlaveID[5] (Address 0x62)
      91. 7.6.91  SlaveID[6] Register
        1. Table 109. SlaveID[6] (Address 0x63)
      92. 7.6.92  SlaveID[7] Register
        1. Table 110. SlaveID[7] (Address 0x64)
      93. 7.6.93  SlaveAlias[0] Register
        1. Table 111. SlaveAlias[0] (Address 0x65)
      94. 7.6.94  SlaveAlias[1] Register
        1. Table 112. SlaveAlias[1] (Address 0x66)
      95. 7.6.95  SlaveAlias[2] Register
        1. Table 113. SlaveAlias[2] (Address 0x67)
      96. 7.6.96  SlaveAlias[3] Register
        1. Table 114. SlaveAlias[3] (Address 0x68)
      97. 7.6.97  SlaveAlias[4] Register
        1. Table 115. SlaveAlias[4] (Address 0x69)
      98. 7.6.98  SlaveAlias[5] Register
        1. Table 116. SlaveAlias[5] (Address 0x6A)
      99. 7.6.99  SlaveAlias[6] Register
        1. Table 117. SlaveAlias[6] (Address 0x6B)
      100. 7.6.100 SlaveAlias[7] Register
        1. Table 118. SlaveAlias[7] (Address 0x6C)
      101. 7.6.101 PORT_CONFIG Register
        1. Table 119. PORT_CONFIG (Address 0x6D)
      102. 7.6.102 BC_GPIO_CTL0 Register
        1. Table 120. BC_GPIO_CTL0 (Address 0x6E)
      103. 7.6.103 BC_GPIO_CTL1 Register
        1. Table 121. BC_GPIO_CTL1 (Address 0x6F)
      104. 7.6.104 RAW10_ID Register
        1. Table 122. RAW10_ID (Address 0x70)
      105. 7.6.105 RAW12_ID Register
        1. Table 123. RAW12_ID (Address 0x71)
      106. 7.6.106 CSI_VC_MAP Register
        1. Table 124. CSI_VC_MAP (Address 0x72)
      107. 7.6.107 LINE_COUNT_HI Register
        1. Table 125. LINE_COUNT_HI (Address 0x73)
      108. 7.6.108 LINE_COUNT_LO Register
        1. Table 126. LINE_COUNT_LO (Address 0x74)
      109. 7.6.109 LINE_LEN_1 Register
        1. Table 127. LINE_LEN_1 (Address 0x75)
      110. 7.6.110 LINE_LEN_0 Register
        1. Table 128. LINE_LEN_0 (Address 0x76)
      111. 7.6.111 FREQ_DET_CTL Register
        1. Table 129. FREQ_DET_CTL (Address 0x77)
      112. 7.6.112 MAILBOX_1 Register
        1. Table 130. MAILBOX_1 (Address 0x78)
      113. 7.6.113 MAILBOX_2 Register
        1. Table 131. MAILBOX_2 (Address 0x79)
      114. 7.6.114 CSI_RX_STS Register
        1. Table 132. CSI_RX_STS (Address 0x7A)
      115. 7.6.115 CSI_ERR_COUNTER Register
        1. Table 133. CSI_ERR_COUNTER (Address 0x7B)
      116. 7.6.116 PORT_CONFIG2 Register
        1. Table 134. PORT_CONFIG2 (Address 0x7C)
      117. 7.6.117 PORT_PASS_CTL Register
        1. Table 135. PORT_PASS_CTL (Address 0x7D)
      118. 7.6.118 SEN_INT_RISE_CTL Register
        1. Table 136. SEN_INT_RISE_CTL (Address 0x7E)
      119. 7.6.119 SEN_INT_FALL_CTL Register
        1. Table 137. SEN_INT_FALL_CTL (Address 0x7F)
      120. 7.6.120 RESERVED Register
        1. Table 138. RESERVED (Address 0xA0 – 0xA4)
      121. 7.6.121 REFCLK_FREQ Register
        1. Table 139. REFCLK_FREQ (Address 0xA5)
      122. 7.6.122 RESERVED Register
        1. Table 140. RESERVED (Address 0xA7 – 0xAF)
      123. 7.6.123 IND_ACC_CTL Register
        1. Table 141. IND_ACC_CTL (Address 0xB0)
      124. 7.6.124 IND_ACC_ADDR Register
        1. Table 142. IND_ACC_ADDR (Address 0xB1)
      125. 7.6.125 IND_ACC_DATA Register
        1. Table 143. IND_ACC_DATA (Address 0xB2)
      126. 7.6.126 BIST Control Register
        1. Table 144. BIST Control (Address 0xB3)
      127. 7.6.127 RESERVED Register
        1. Table 145. RESERVED (Address 0xB4)
      128. 7.6.128 RESERVED Register
        1. Table 146. RESERVED (Address 0xB5)
      129. 7.6.129 RESERVED Register
        1. Table 147. RESERVED (Address 0xB6)
      130. 7.6.130 RESERVED Register
        1. Table 148. RESERVED (Address 0xB7)
      131. 7.6.131 MODE_IDX_STS Register
        1. Table 149. MODE_IDX_STS (Address 0xB8)
      132. 7.6.132 LINK_ERROR_COUNT Register
        1. Table 150. LINK_ERROR_COUNT (Address 0xB9)
      133. 7.6.133 FPD3_ENC_CTL Register
        1. Table 151. FPD3_ENC_CTL (Address 0xBA)
      134. 7.6.134 RESERVED Register
        1. Table 152. RESERVED (Address 0xBB)
      135. 7.6.135 FV_MIN_TIME Register
        1. Table 153. FV_MIN_TIME (Address 0xBC)
      136. 7.6.136 RESERVED Register
        1. Table 154. RESERVED (Address 0xBD)
      137. 7.6.137 GPIO_PD_CTL Register
        1. Table 155. GPIO_PD_CTL (Address 0xBE)
      138. 7.6.138 RESERVED Register
        1. Table 156. RESERVED (Address 0xBF)
      139. 7.6.139 PORT_DEBUG Register
        1. Table 157. PORT_DEBUG (Address 0xD0)
      140. 7.6.140 RESERVED Register
      141. 7.6.141 AEQ_CTL2 Register
        1. Table 159. AEQ_CTL2 (Address 0xD2)
      142. 7.6.142 AEQ_STATUS Register
        1. Table 160. AEQ_STATUS (Address 0xD3)
      143. 7.6.143 ADAPTIVE EQ BYPASS Register
        1. Table 161. ADAPTIVE EQ BYPASS (Address 0xD4)
      144. 7.6.144 AEQ_MIN_MAX Register
        1. Table 162. AEQ_MIN_MAX (Address 0xD5)
      145. 7.6.145 RESERVED Register
        1. Table 163. RESERVED (Address 0xD6)
      146. 7.6.146 RESERVED Register
        1. Table 164. RESERVED (Address 0xD7)
      147. 7.6.147 PORT_ICR_HI Register
        1. Table 165. PORT_ICR_HI (Address 0xD8)
      148. 7.6.148 PORT_ICR_LO Register
        1. Table 166. PORT_ICR_LO (Address 0xD9)
      149. 7.6.149 PORT_ISR_HI Register
        1. Table 167. PORT_ISR_HI (Address 0xDA)
      150. 7.6.150 PORT_ISR_LO Register
        1. Table 168. PORT_ISR_LO (Address 0xDB)
      151. 7.6.151 FC_GPIO_STS Register
        1. Table 169. FC_GPIO_STS (Address 0xDC)
      152. 7.6.152 FC_GPIO_ICR Register
        1. Table 170. FC_GPIO_ICR (Address 0xDD)
      153. 7.6.153 SEN_INT_RISE_STS Register
        1. Table 171. SEN_INT_RISE_STS (Address 0xDE)
      154. 7.6.154 SEN_INT_FALL_STS Register
        1. Table 172. SEN_INT_FALL_STS (Address 0xDF)
      155. 7.6.155 FPD3_RX_ID0 Register
        1. Table 173. FPD3_RX_ID0 (Address 0xF0)
      156. 7.6.156 FPD3_RX_ID1 Register
        1. Table 174. FPD3_RX_ID1 (Address 0xF1)
      157. 7.6.157 FPD3_RX_ID2 Register
        1. Table 175. FPD3_RX_ID2 (Address 0xF2)
      158. 7.6.158 FPD3_RX_ID3 Register
        1. Table 176. FPD3_RX_ID3 (Address 0xF3)
      159. 7.6.159 FPD3_RX_ID4 Register
        1. Table 177. FPD3_RX_ID4 (Address 0xF4)
      160. 7.6.160 FPD3_RX_ID5 Register
        1. Table 178. FPD3_RX_ID5 (Address 0xF5)
      161. 7.6.161 I2C_RX0_ID Register
        1. Table 179. I2C_RX0_ID (Address 0xF8)
      162. 7.6.162 I2C_RX1_ID Register
        1. Table 180. I2C_RX1_ID (Address 0xF9)
      163. 7.6.163 RESERVED Register
        1. Table 181. RESERVED (Address 0xFA)
      164. 7.6.164 RESERVED Register
        1. Table 182. RESERVED (Address 0xFB)
      165. 7.6.165 Indirect Access Registers
      166. 7.6.166 Reserved Register
        1. Table 184. Reserved (Indirect Address Page 0x00; Register 0x00)
      167. 7.6.167 PGEN_CTL Register
        1. Table 185. PGEN_CTL (Indirect Address Page 0x00; Register 0x01)
      168. 7.6.168 PGEN_CFG Register
      169. 7.6.169 PGEN_CSI_DI Register
        1. Table 187. PGEN_CSI_DI (Indirect Address Page 0x00; Register 0x03)
      170. 7.6.170 PGEN_LINE_SIZE1 Register
        1. Table 188. PGEN_LINE_SIZE1 (Indirect Address Page 0x00; Register 0x04)
      171. 7.6.171 PGEN_LINE_SIZE0 Register
        1. Table 189. PGEN_LINE_SIZE0 (Indirect Address Page 0x00; Register 0x05)
      172. 7.6.172 PGEN_BAR_SIZE1 Register
        1. Table 190. PGEN_BAR_SIZE1 (Indirect Address Page 0x00; Register 0x06)
      173. 7.6.173 PGEN_BAR_SIZE0 Register
        1. Table 191. PGEN_BAR_SIZE0 (Indirect Address Page 0x00; Register 0x07)
      174. 7.6.174 PGEN_ACT_LPF1 Register
        1. Table 192. PGEN_ACT_LPF1 (Indirect Address Page 0x00; Register 0x08)
      175. 7.6.175 PGEN_ACT_LPF0 Register
        1. Table 193. PGEN_ACT_LPF0 (Indirect Address Page 0x00; Register 0x09)
      176. 7.6.176 PGEN_TOT_LPF1 Register
        1. Table 194. PGEN_TOT_LPF1 (Indirect Address Page 0x00; Register 0x0A)
      177. 7.6.177 PGEN_TOT_LPF0 Register
        1. Table 195. PGEN_TOT_LPF0 (Indirect Address Page 0x00; Register 0x0B)
      178. 7.6.178 PGEN_LINE_PD1 Register
        1. Table 196. PGEN_LINE_PD1 (Indirect Address Page 0x00; Register 0x0C)
      179. 7.6.179 PGEN_LINE_PD0 Register
        1. Table 197. PGEN_LINE_PD0 (Indirect Address Page 0x00; Register 0x0D)
      180. 7.6.180 PGEN_VBP Register
        1. Table 198. PGEN_VBP (Indirect Address Page 0x00; Register 0x0E)
      181. 7.6.181 PGEN_VFP Register
        1. Table 199. PGEN_VFP (Indirect Address Page 0x00; Register 0x0F)
      182. 7.6.182 PGEN_COLOR0 Register
        1. Table 200. PGEN_COLOR0 (Indirect Address Page 0x00; Register 0x10)
      183. 7.6.183 PGEN_COLOR1 Register
        1. Table 201. PGEN_COLOR1 (Indirect Address Page 0x00; Register 0x11)
      184. 7.6.184 PGEN_COLOR2 Register
        1. Table 202. PGEN_COLOR2 (Indirect Address Page 0x00; Register 0x12)
      185. 7.6.185 PGEN_COLOR3 Register
        1. Table 203. PGEN_COLOR3 (Indirect Address Page 0x00; Register 0x13)
      186. 7.6.186 PGEN_COLOR4 Register
        1. Table 204. PGEN_COLOR4 (Indirect Address Page 0x00; Register 0x14)
      187. 7.6.187 PGEN_COLOR5 Register
        1. Table 205. PGEN_COLOR5 (Indirect Address Page 0x00; Register 0x15)
      188. 7.6.188 PGEN_COLOR6 Register
        1. Table 206. PGEN_COLOR6 (Indirect Address Page 0x00; Register 0x16)
      189. 7.6.189 PGEN_COLOR7 Register
        1. Table 207. PGEN_COLOR7 (Indirect Address Page 0x00; Register 0x17)
      190. 7.6.190 PGEN_COLOR8 Register
        1. Table 208. PGEN_COLOR8 (Indirect Address Page 0x00; Register 0x18)
      191. 7.6.191 PGEN_COLOR9 Register
        1. Table 209. PGEN_COLOR9 (Indirect Address Page 0x00; Register 0x19)
      192. 7.6.192 PGEN_COLOR10 Register
        1. Table 210. PGEN_COLOR10 (Indirect Address Page 0x00; Register 0x1A)
      193. 7.6.193 PGEN_COLOR11 Register
        1. Table 211. PGEN_COLOR11 (Indirect Address Page 0x00; Register 0x1B)
      194. 7.6.194 PGEN_COLOR12 Register
        1. Table 212. PGEN_COLOR12 (Indirect Address Page 0x00; Register 0x1C)
      195. 7.6.195 PGEN_COLOR13 Register
        1. Table 213. PGEN_COLOR13 (Indirect Address Page 0x00; Register 0x1D)
      196. 7.6.196 PGEN_COLOR14 Register
        1. Table 214. PGEN_COLOR14 (Indirect Address Page 0x00; Register 0x1E)
      197. 7.6.197 RESERVED Register
        1. Table 215. RESERVED (Indirect Address Page 0x00; Register 0x1F)
      198. 7.6.198 CSI0_TCK_PREP Register
        1. Table 216. CSI0_TCK_PREP (Indirect Address Page 0x00; Register 0x40)
      199. 7.6.199 CSI0_TCK_ZERO Register
        1. Table 217. CSI0_TCK_ZERO (Indirect Address Page 0x00; Register 0x41)
      200. 7.6.200 CSI0_TCK_TRAIL Register
        1. Table 218. CSI0_TCK_TRAIL (Indirect Address Page 0x00; Register 0x42)
      201. 7.6.201 CSI0_TCK_POST Register
        1. Table 219. CSI0_TCK_POST (Indirect Address Page 0x00; Register 0x43)
      202. 7.6.202 CSI0_THS_PREP Register
        1. Table 220. CSI0_THS_PREP (Indirect Address Page 0x00; Register 0x44)
      203. 7.6.203 CSI0_THS_ZERO Register
        1. Table 221. CSI0_THS_ZERO (Indirect Address Page 0x00; Register 0x45)
      204. 7.6.204 CSI0_THS_TRAIL Register
        1. Table 222. CSI0_THS_TRAIL (Indirect Address Page 0x00; Register 0x46)
      205. 7.6.205 CSI0_THS_EXIT Register
        1. Table 223. CSI0_THS_EXIT (Indirect Address Page 0x00; Register 0x47)
      206. 7.6.206 CSI0_TPLX Register
        1. Table 224. CSI0_TPLX (Indirect Address Page 0x00; Register 0x48)
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 System
      2. 8.1.2 Power Over Coax
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 System Examples
  9. 9 Power Supply Recommendations
    1. 9.1 VDD and VDDIO Power Supply
    2. 9.2 Power-Up Sequencing
      1. 9.2.1 PDB Pin
      2. 9.2.2 System Initialization
  10. 10Layout
    1. 10.1 PCB Layout Guidelines
      1. 10.1.1 Ground
      2. 10.1.2 Routing FPD-Link III Signal Traces and PoC Filter
      3. 10.1.3 Routing CSI-2 Signal Traces
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • AEC-Q100 Qualified for Automotive Applications:
    • Device Temperature Grade 2: –40℃ to +105℃ Ambient Operating Temperature Range
  • 2.528 Gbps CSI-2 Video Bandwidth Per Channel
  • MIPI DPHY Version 1.2 / CSI-2 Version 1.3 Compliant
    • CSI-2 Output Ports
    • Supports 1, 2, 4 Data Lanes
    • CSI-2 Data Rate Scalable for 400 Mbps / 800 Mbps / 1.5 Gbps / 1.6 Gbps each Data Lane
    • Programmable Data Types
    • Four Virtual Channels
    • ECC and CRC Generation
  • 2x2 Output Replication Mode
  • Ultra-Low Data and Control Path Latency
  • Supports Single-Ended Coaxial or Shielded Twisted-Pair (STP) Cable
  • Adaptive Receive Equalization
  • I2C With Fast-Mode Plus up to 1 Mbps
  • Flexible GPIOs for Camera Diagnostics
  • Compatible With DS90UB935-Q1, DS90UB933-Q1 and DS90UB913A-Q1 Serializers
  • Line Fault Detection and Advanced Diagnostics
  • ISO 10605 and IEC 61000-4-2 ESD Compliant