SNLS553 December   2016 FPC401


  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Description (continued)
  6. 6Device and Documentation Support
    1. 6.1 Documentation Support
      1. 6.1.1 Related Documentation
    2. 6.2 Receiving Notification of Documentation Updates
    3. 6.3 Community Resources
    4. 6.4 Trademarks
    5. 6.5 Electrostatic Discharge Caution
    6. 6.6 Glossary
  7. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information


  • Supports Control Signal Management and I2C Aggregation Across Four Ports
  • Combine Multiple FPC401s to Control 56 Total Ports Through a Single Host Interface
  • Eliminates Need for Discrete I2C Muxes, LED Drivers, and High-Pin-Count FPGA/CPLD Control Devices
  • Reduces PCB Routing Complexity by Handling All Low-Speed Control Signals Close to the Port
  • Selectable I2C (Up to 1 MHz) or SPI (Up to 10 MHz) Host Control Interface
  • Automatic Pre-Fetching of Critical, User-Specified Data From the Modules
  • Low Single-Port and Multi-Port Read/Write Latency: <50 µs for SPI Mode, <400 µs for I2C Mode
  • Broadcast Mode Allows Writes to All Ports Simultaneously Across All FPC401 Controllers
  • Advanced LED Features for Port Status Indication, Including Programmable Blinking and Dimming
  • Customizable Interrupt Events
  • Separate Host-Side I/O Voltage: 1.8-V to 3.3-V
  • Small QFN Package Enabling Placement on Bottom Side of PCB Underneath Ports


  • ToR/Aggregation/Core Switch and Router SFP+/QSFP+ Port Control
  • SAS External Cable Management Interface Control
  • Video Switch & Router SFP+/QSFP+ Port Control


The FPC401 quad port controller serves as a low-speed signal aggregator for common port types such as SFP+, QSFP+, and SAS. The FPC401 aggregates all low-speed control and I2C signals across four ports and presents a single easy-to-use management interface to the host (I2C or SPI). Multiple FPC401s can be used in high-port-count applications with one common control interface to the host. The FPC401 is designed to allow placement on the bottom side of the PCB, underneath the press fit connector, to simplify routing. This localized control of the ports’ low-speed signals cuts system BOM cost by enabling the use of smaller IO count control devices (FPGAs, CPLDs, MCUs) and by reducing routing layer congestion.

Device Information(1)

FPC401 QFN (56) 5.00 mm × 11.00 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Simplified Block Diagram

FPC401 fpc_simplified_block_diagram.gif