8.1.1 Analog Inputs

An equivalent circuit for one of the input channels of the ADC128S052 is shown in Figure 37. Diodes D1 and D2 provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to V_A. Going beyond this range causes the ESD diodes to conduct and result in erratic operation.

The capacitor C1 in Figure 37 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1 is the on resistance of the multiplexer and track or hold switch and is typically 500 Ω. Capacitor C2 is the ADC128S052 sampling capacitor and is typically 30 pF. The ADC128S052 delivers best performance when driven by a low-impedance source (less than 100 Ω). This is especially important when using the ADC128S052 to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or low-pass filter which reduces harmonics and noise in the input. These filters are often referred to as anti-aliasing filters.

Figure 37. Equivalent Input Circuit

8.1.2 Digital Inputs and Outputs

The digital inputs (SCLK, CS, and DIN) of the ADC128S052 have an operating range of 0 V to V_A. They are not prone to latch-up and may be asserted before the digital supply (V_D) without any risk. The digital output (DOUT) operating range is controlled by V_D. The output high voltage is V_D – 0.5 V (minimum) while the output low voltage is 0.4 V (maximum).

8.2.1 Design Requirements

A positive supply-only data acquisition system capable of digitizing signals ranging 0 to 5 V, BW = 10 kHz, and a throughput of 125 kSPS.

The ADC128S052 has to interface to a microcontroller with the supply is set at 3.3 V.

8.2.2 Detailed Design Procedure

The signal range requirement forces the design to use 5-V analog supply at V_A, analog supply. This follows from the fact that V_A is also a reference potential for the ADC.

The requirement of interfacing to the microcontroller which is powered by a 3.3-V supply, forces the choice of
3.3 V as a V_D supply.

Sampling is in fact a modulation process which may result in aliasing of the input signal, if the input signal is not adequately band limited. The maximum sampling rate of the ADC128S052 when all channels are enabled is, Fs is calculated by Equation 2:

Equation 2.

Note that faster sampling rates can be achieved when fewer channels are sampled. Single channel can be sampled at the maximum rate of:

Equation 3.

In order to avoid the aliasing the Nyquist criterion has to be met:

Equation 4.

Therefore it is necessary to place anti-aliasing filters at all inputs of the ADC. These filters may be single-pole low-pass filters. The pole locations need to satisfy, assuming all channels sampled in sequence, Equation 5 and Equation 6:

Equation 5.

Equation 6.

With F_SCLK = 16 MHz, a good choice for the single pole filter is:

• R = 100
• C = 33 nF

This reduces the input BW_signal = 48 kHz. The capacitor at the INx input of the device provides not only the filtering of the input signal, but it also absorbs the charge kick-back from the ADC. The kick-back is the result of the internal switches opening at the end of the acquisition period.

The V_A and V_D sources are already separated in this example, due to the design requirements. This also benefits the overall performance of the ADC, as the potentially noisy V_D supply does not contaminate the V_A. In the same vain, further consideration could be given to the SPI interface, especially when the master microcontroller is capable of producing fast rising edges on the digital bus signals. Inserting small resistances in the digital signal path may help in reducing the ground bounce, and thus improve the overall noise performance of the system.

Take care when the signal source is capable of producing voltages beyond V_A. In such instances the internal ESD diodes may start conducting. The ESD diodes are not intended as input signal clamps. To provide the desired clamping action use Schottky diodes as shown in Figure 38.

8.2.3 Application Curve

Figure 39. Typical Performance