SNAS480N May   2010  – August 2015 ADC12D1000 , ADC12D1600

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Static Converter
    6. 6.6  Electrical Characteristics: Dynamic Converter
    7. 6.7  Electrical Characteristics: Analog Input/Output and Reference
    8. 6.8  Electrical Characteristics: I-Channel To Q-Channel
    9. 6.9  Electrical Characteristics: Converter and Sampling Clock
    10. 6.10 Electrical Characteristics: Autosync Feature
    11. 6.11 Electrical Characteristics: Digital Control and Output Pin
    12. 6.12 Electrical Characteristics: Power Supply
    13. 6.13 Electrical Characteristics: AC
    14. 6.14 Timing Requirements: Serial Port Interface
    15. 6.15 Timing Requirements: Calibration
    16. 6.16 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Control and Adjust
        1. 7.3.1.1 AC-DC-Coupled Mode
        2. 7.3.1.2 Input Full-Scale Range Adjust
        3. 7.3.1.3 Input Offset Adjust
        4. 7.3.1.4 DES Timing Adjust
        5. 7.3.1.5 Sampling Clock Phase Adjust
      2. 7.3.2 Output Control and Adjust
        1. 7.3.2.1 DDR Clock Phase
        2. 7.3.2.2 LVDS Output Differential Voltage
        3. 7.3.2.3 LVDS Output Common-Mode Voltage
        4. 7.3.2.4 Output Formatting
        5. 7.3.2.5 Test Pattern Mode
        6. 7.3.2.6 Time Stamp
      3. 7.3.3 Calibration Feature
        1. 7.3.3.1 Calibration Control Pins and Bits
        2. 7.3.3.2 How to Execute a Calibration
        3. 7.3.3.3 Power-On Calibration
        4. 7.3.3.4 On-Command Calibration
        5. 7.3.3.5 Calibration Adjust
        6. 7.3.3.6 Read/Write Calibration Settings
        7. 7.3.3.7 Calibration and Power-Down
        8. 7.3.3.8 Calibration and the Digital Outputs
      4. 7.3.4 Power Down
    4. 7.4 Device Functional Modes
      1. 7.4.1 DES/Non-DES Mode
      2. 7.4.2 Demux/Non-Demux Mode
    5. 7.5 Programming
      1. 7.5.1 Control Modes
        1. 7.5.1.1 Non-Extended Control Mode
          1. 7.5.1.1.1  Dual Edge Sampling Pin (DES)
          2. 7.5.1.1.2  Non-Demultiplexed Mode Pin (NDM)
          3. 7.5.1.1.3  Dual Data Rate Phase Pin (DDRPH)
          4. 7.5.1.1.4  Calibration Pin (CAL)
          5. 7.5.1.1.5  Calibration Delay Pin (CALDLY)
          6. 7.5.1.1.6  Power-Down I-Channel Pin (PDI)
          7. 7.5.1.1.7  Power-Down Q-Channel Pin (PDQ)
          8. 7.5.1.1.8  Test Pattern Mode Pin (TPM)
          9. 7.5.1.1.9  Full-Scale Input Range Pin (FSR)
          10. 7.5.1.1.10 AC-DC-Coupled Mode Pin (VCMO)
          11. 7.5.1.1.11 LVDS Output Common-Mode Pin (VBG)
        2. 7.5.1.2 Extended Control Mode
          1. 7.5.1.2.1 The Serial Interface
    6. 7.6 Register Maps
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 The Analog Inputs
        1. 8.1.1.1 Acquiring the Input
        2. 8.1.1.2 Driving the ADC in DES Mode
        3. 8.1.1.3 FSR and the Reference Voltage
        4. 8.1.1.4 Out-of-Range Indication
        5. 8.1.1.5 Maximum Input Range
        6. 8.1.1.6 AC-Coupled Input Signals
        7. 8.1.1.7 DC-Coupled Input Signals
        8. 8.1.1.8 Single-Ended Input Signals
      2. 8.1.2 The Clock Inputs
        1. 8.1.2.1 CLK Coupling
        2. 8.1.2.2 CLK Frequency
        3. 8.1.2.3 CLK Level
        4. 8.1.2.4 CLK Duty Cycle
        5. 8.1.2.5 CLK Jitter
        6. 8.1.2.6 CLK Layout
      3. 8.1.3 The LVDS Outputs
        1. 8.1.3.1 Common-Mode and Differential Voltage
        2. 8.1.3.2 Output Data Rate
        3. 8.1.3.3 Terminating Unused LVDS Output Pins
      4. 8.1.4 Synchronizing Multiple ADC12D1x00s in a System
        1. 8.1.4.1 Autosync Feature
        2. 8.1.4.2 DCLK Reset Feature
      5. 8.1.5 Recommended System Chips
        1. 8.1.5.1 Temperature Sensor
        2. 8.1.5.2 Clocking Device
        3. 8.1.5.3 Amplifiers for the Analog Input
        4. 8.1.5.4 Balun Recommendations for Analog Input
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
    1. 9.1 System Power-On Considerations
      1. 9.1.1 Power-On, Configuration, and Calibration
      2. 9.1.2 Power-On and Data Clock (Dclk)
    2. 9.2 Supply Voltage
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Power Planes
      2. 10.1.2 Bypass Capacitors
      3. 10.1.3 Ground Planes
      4. 10.1.4 Power System Example
    2. 10.2 Layout Example
    3. 10.3 Thermal Management
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
        1. 11.1.1.1 Specification Definitions
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Related Links
    4. 11.4 Community Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

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サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply Voltage (VA, VTC, VDR, VE) 2.2 V
Supply Difference
max(VA/TC/DR/E) - min(VA/TC/DR/E)
0 100 mV
Voltage on Any Input Pin
(except VIN+/-)
–0.15 VA + 0.15 V
VIN+/- Voltage Range –0.5 2.5 V
Ground Difference
max(GNDTC/DR/E) - min(GNDTC/DR/E)
0 100 mV
Input Current at Any Pin(2) –50 50 mA
ADC12D1000 Package Power Dissipation at TA ≤ 75°C(2) 4.06 W
ADC12D1600 Package Power Dissipation at TA ≤ 65°C(2) 4.37 W
Storage Temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) When the input voltage at any pin exceeds the power supply limits, that is, less than GND or greater than VA, the current at that pin should be limited to 50 mA. In addition, overvoltage at a pin must adhere to the maximum voltage limits. Simultaneous overvoltage at multiple pins requires adherence to the maximum package power dissipation limits. These dissipation limits are calculated using JEDEC JESD51-7 thermal model. Higher dissipation may be possible based on specific customer thermal situation and specified package thermal resistances from junction to case.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
Machine Model ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN NOM MAX UNIT
TA Ambient Temperature ADC12D1000 (Standard JEDEC thermal model) –40 75 °C
ADC12D1600 (Standard JEDEC thermal model) –40 65 °C
ADC12D1x00 (Enhanced thermal model or heatsink) –40 85 °C
TJ Junction Temperature Range(4) ADC12D1000 Junction Temperature Range 140 °C
ADC12D1600 Junction Temperature Range 135 °C
Supply Voltage (VA, VTC, VE) 1.8 2 V
Driver Supply Voltage (VDR) 1.8 VA V
VIN+/- Voltage Range(2) (DC-coupled) –0.4 2.4 V
VIN+/- Differential Voltage(3) (DC-coupled at 100% duty cycle) 1 V
(DC-coupled at 20% duty cycle) 2
(DC-coupled at 10% duty cycle) 2.8
VIN+/- Current Range(3) (AC-coupled) –50 50 mA peak
VIN+/- Power (maintaining common-mode voltage, AC-coupled) 15.3 dBm
(not maintaining common-mode voltage, AC-coupled) 17.1
Ground Difference
max(GNDTC/DR/E)
-min(GNDTC/DR/E)
0 V
CLK+/- Voltage Range 0 VA V
Differential CLK Amplitude 0.4 2 VP-P
VCMI Common Mode Input Voltage VCMO – 150 VCMO +150 mV
(1) All voltages are measured with respect to GND = GNDTC = GNDDR = GNDE = 0 V, unless otherwise specified.
(2) Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive.
(3) This rating is intended for DC-coupled applications; the voltages listed may be safely applied to VIN+/- for the life-time duty-cycle of the part.
(4) Applies only to maximum operating speed.

6.4 Thermal Information

THERMAL METRIC(1) ADC12D1000, ADC12D1600 UNIT
NXA (BGA)
292 PINS
RθJA Junction-to-ambient thermal resistance 16 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 2.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics: Static Converter

Unless otherwise specified, the following apply after calibration for VA = VDR = VTC = VE = 1.9 V; I- and Q-channels, AC-coupled, unused channel terminated to AC ground, FSR Pin = High; CL = 10 pF; Differential, AC coupled Sine Wave Sampling Clock, fCLK = 1 or 1.6 GHz at 0.5 VP-P with 50% duty cycle (as specified); VBG = Floating; Non-Extended Control Mode; Rext = Rtrim = 3300 Ω ± 0.1%; Analog Signal Source Impedance = 100-Ω Differential; 1:2 Demultiplex Non-DES Mode; Duty Cycle Stabilizer on. All other limits TA = 25°C, unless otherwise noted.(1)(2)(3)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution with No Missing Codes TA = TMIN to TMAX 12 bits
INL Integral Non-Linearity
(Best fit)
1-MHz DC-coupled over-ranged sine wave TA = 25°C ±2.5 LSB
TA = TMIN to TMAX ±4.8
DNL Differential Non-Linearity 1-MHz DC-coupled over-ranged sine wave TA = 25°C ±0.4 LSB
TA = TMIN to TMAX ±0.9
VOFF Offset Error 5 LSB
VOFF_ADJ Input Offset Adjustment Range Extended Control Mode ±45 mV
PFSE Positive Full-Scale Error See(4). TA = TMIN to TMAX ±25 mV
NFSE Negative Full-Scale Error See(4). TA = TMIN to TMAX ±25 mV
Out-of-Range Output Code(5) (VIN+) − (VIN−) > + Full Scale, TA = TMIN to TMAX 4095
(VIN+) − (VIN−) < − Full Scale, TA = TMIN to TMAX 0
(1) The analog inputs, labeled "I/O", are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device). See the following figure.ADC12D1000 ADC12D1600 30091604.gif
(2) To ensure accuracy, it is required that VA, VTC, VE and VDR be well-bypassed. Each supply pin must be decoupled with separate bypass capacitors.
(3) Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are ensured to TI's AOQL (Average Outgoing Quality Level).
(4) Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device, therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 8. For relationship between Gain Error and Full-Scale Error, see Specification Definitions for Gain Error.
(5) This parameter is specified by design and is not tested in production.

6.6 Electrical Characteristics: Dynamic Converter

TA = 25°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FPBW Full Power Bandwidth Non-DES Mode 2.8 GHz
DESI, DESQ Mode 1.25 GHz
DESIQ Mode 1.75 GHz
Gain Flatness NON-DES MODE
D.C. to Fs/2 ADC12D1000 0.35 dB
ADC12D1600 0.5
D.C. to Fs ADC12D1000 0.5 dB
ADC12D1600 1
DESI, DESQ MODE
D.C. to Fs/2 ADC12D1000 2.4 dB
ADC12D1600 4
DESIQ MODE
D.C. to Fs/2 ADC12D1000 1.9 dB
ADC12D1600 2
CER Code Error Rate 10–18 Error/Sample
NPR Noise Power Ratio See(1) ADC12D1000 49.5 dB
ADC12D1600 48.5
IMD3 3rd order Intermodulation Distortion FIN1 = 1212.52 MHz at -7dBFS ADC12D1000 –66 dBFS
ADC12D1600 –63
FIN2 = 1217.52 MHz at -7dBFS
DESIQ Mode
ADC12D1000 –59 dBc
ADC12D1600 –56
Noise Floor Density 50Ω single-ended termination, DES Mode ADC12D1000 –152.6 dBm/Hz
ADC12D1600 –153.6
ADC12D1000 –151.6 dBFS/Hz
ADC12D1600 –152.6
Wideband input, DES Mode(2) ADC12D1000 –151.5 dBm/Hz
ADC12D1600 –152.6
ADC12D1000 –150.5 dBFS/Hz
ADC12D1600 –151.6
NON-DES MODE(2)(2)
ENOB Effective Number of Bits AIN = 125 MHz at –0.5 dBFS ADC12D1000 9.6 bits
ADC12D1600 9.4
AIN = 248 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
9.5
8.7
bits
ADC12D1600
TA = TMIN to TMAX
9.4
8.6
AIN = 498 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
9.4
8.7
bits
ADC12D1600
TA = TMIN to TMAX
9.3
8.6
AIN = 998 MHz at –0.5 dBFS 8.9 bits
AIN = 1448 MHz at –0.5 dBFS 8.6 bits
SINAD Signal-to-Noise Plus Distortion Ratio AIN = 125 MHz at –0.5 dBFS ADC12D1000 59.7 dB
ADC12D1600 58.2
AIN = 248 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
59
54.1
dB
ADC12D1600
TA = TMIN to TMAX
58
53.5
AIN = 498 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
58.2
54.1
dB
ADC12D1600
TA = TMIN to TMAX
57.8
53.5
AIN = 998 MHz at –0.5 dBFS ADC12D1000 55.4 dB
ADC12D1600 55.1
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 53.6 dB
ADC12D1600 53.8
SNR Signal-to-Noise Ratio AIN = 125 MHz at –0.5 dBFS ADC12D1000 60.2 dB
ADC12D1600 58.5
AIN = 248 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
59.7
55.1
dB
ADC12D1600
TA = TMIN to TMAX
58.7
54.6
AIN = 498 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
58.7
55.1
dB
ADC12D1600
TA = TMIN to TMAX
58.5
54.6
AIN = 998 MHz at –0.5 dBFS ADC12D1000 56.3 dB
ADC12D1600 56.5
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 54.1 dB
ADC12D1600 55
THD Total Harmonic Distortion AIN = 125 MHz at –0.5 dBFS ADC12D1000 –68.7 dB
ADC12D1600 –70.3
AIN = 248 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
–67
–61
dB
ADC12D1600
TA = TMIN to TMAX
–66.6
–60
AIN = 498 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
–67.4
–61
dB
ADC12D1600
TA = TMIN to TMAX
–66
–60
AIN = 998 MHz at –0.5 dBFS ADC12D1000 –62.9 dB
ADC12D1600 –60.8
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 –63 dB
ADC12D1600 –60
2nd Harm Second Harmonic Distortion AIN = 125 MHz at –0.5 dBFS ADC12D1000 –75.7 dBc
ADC12D1600 –75
AIN = 248 MHz at –0.5 dBFS ADC12D1000 –75.7 dBc
ADC12D1600 –80
AIN = 498 MHz at –0.5 dBFS ADC12D1000 –79.8 dBc
ADC12D1600 –71
AIN = 998 MHz at –0.5 dBFS ADC12D1000 –70 dBc
ADC12D1600 –73
AIN = 1448 MHz at –0.5 dBFS –67 dBc
3rd Harm Third Harmonic Distortion AIN = 125 MHz at –0.5 dBFS ADC12D1000 –71 dBc
ADC12D1600 –74
AIN = 248 MHz at –0.5 dBFS ADC12D1000 –68.4 dBc
ADC12D1600 –68
AIN = 498 MHz at –0.5 dBFS ADC12D1000 –68.7 dBc
ADC12D1600 –69
AIN = 998 MHz at –0.5 dBFS ADC12D1000 –66 dBc
ADC12D1600 –62
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 –67 dBc
ADC12D1600 –61
SFDR Spurious-Free Dynamic Range AIN = 125 MHz at –0.5 dBFS ADC12D1000 71 dBc
ADC12D1600 70.3
AIN = 248 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
68.4
61
dBc
ADC12D1600
TA = TMIN to TMAX
68
60
AIN = 498 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
68.7
61
dBc (min)
ADC12D1600
TA = TMIN to TMAX
68.2
60
AIN = 998 MHz at –0.5 dBFS ADC12D1000 66 dBc
ADC12D1600 62
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 67 dBc
ADC12D1600 61.9
DES MODE(2)(2)(2)
ENOB Effective Number of Bits AIN = 125 MHz at –0.5 dBFS ADC12D1000 9.5 bits
ADC12D1600 9.4
AIN = 248 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
9.4
8.7
bits
ADC12D1600
TA = TMIN to TMAX
9.2
8.6
AIN = 498 MHz at –0.5 dBFS ADC12D1000 9.2 bits
ADC12D1600 9.1
AIN = 998 MHz at –0.5 dBFS ADC12D1000 8.8 bits
ADC12D1600 8.5
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 8.6 bits
ADC12D1600 8.5
SINAD Signal-to-Noise Plus Distortion Ratio AIN = 125 MHz at –0.5 dBFS ADC12D1000 59 dB
ADC12D1600 58.2
AIN = 248 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
58.6
54
dB
ADC12D1600
TA = TMIN to TMAX
57
53.5
AIN = 498 MHz at –0.5 dBFS ADC12D1000 57.3 dB
ADC12D1600 56.9
AIN = 998 MHz at –0.5 dBFS ADC12D1000 54.5 dB
ADC12D1600 52.7
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 53.9 dB
ADC12D1600 52.7
SNR Signal-to-Noise Ratio AIN = 125 MHz at –0.5 dBFS ADC12D1000 59.2 dB
ADC12D1600 58.6
AIN = 248 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
58.9
55.3
dB
ADC12D1600
TA = TMIN to TMAX
57.9
54.6
AIN = 498 MHz at –0.5 dBFS ADC12D1000 58.3 dB
ADC12D1600 57.6
AIN = 998 MHz at –0.5 dBFS ADC12D1000 55.9 dB
ADC12D1600 53.6
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 54.2 dB
ADC12D1600 53.3
THD Total Harmonic Distortion AIN = 125 MHz at –0.5 dBFS ADC12D1000 –74 dB
ADC12D1600 –68.2
AIN = 248 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
–71.2
–60
dB
ADC12D1600
TA = TMIN to TMAX
–64.6
–60
AIN = 498 MHz at –0.5 dBFS ADC12D1000 –63.8 dB
ADC12D1600 –66.3
AIN = 998 MHz at –0.5 dBFS ADC12D1000 –60 dB
ADC12D1600 –60
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 –65 dB
ADC12D1600 –61.7
2nd Harm Second Harmonic Distortion AIN = 125 MHz at –0.5 dBFS ADC12D1000 –82 dBc
ADC12D1600 –77.3
AIN = 248 MHz at –0.5 dBFS ADC12D1000 –82 dBc
ADC12D1600 –82.7
AIN = 498 MHz at –0.5 dBFS ADC12D1000 –72 dBc
ADC12D1600 –71.6
AIN = 998 MHz at –0.5 dBFS ADC12D1000 –63.2 dBc
ADC12D1600 –63
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 –75 dBc
ADC12D1600 –75.6
3rd Harm Third Harmonic Distortion AIN = 125 MHz at –0.5 dBFS ADC12D1000 –82 dBc
ADC12D1600 –69.8
AIN = 248 MHz at –0.5 dBFS ADC12D1000 –73 dBc
ADC12D1600 –65.3
AIN = 498 MHz at –0.5 dBFS ADC12D1000 –65 dBc
ADC12D1600 –67.3
AIN = 998 MHz at –0.5 dBFS ADC12D1000 –65 dBc
ADC12D1600 –63
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 –67 dBc
ADC12D1600 –62.4
SFDR Spurious-Free Dynamic Range AIN = 125 MHz at –0.5 dBFS ADC12D1000 69 dBc
ADC12D1600 69.8
AIN = 248 MHz at –0.5 dBFS ADC12D1000
TA = TMIN to TMAX
69
60
dBc
ADC12D1600
TA = TMIN to TMAX
65.3
60
AIN = 498 MHz at –0.5 dBFS ADC12D1000 65 dBc
ADC12D1600 67.3
AIN = 998 MHz at –0.5 dBFS ADC12D1000 64 dBc
ADC12D1600 60.2
AIN = 1448 MHz at –0.5 dBFS ADC12D1000 66 dBc
ADC12D1600 60
(1) The NPR was measured using an Agilent N6030A Arbitrary Waveform Generator (ARB) to generate the input signal. See the Wideband Performance for an example spectrum. The "noise" portion of the signal was created by tones spaced at 500 kHz and the "notch" was a 25-MHz absence of tones centered at 320 MHz. The bandwidth of this equipment is only 500 MHz, so the final reported NPR was extrapolated from the measured NPR as if the entire Nyquist band were occupied with noise.
(2) The Noise Floor was measured for two conditions: the analog input terminated with 50 Ω, and in the presence of a 500-MHz wideband noise signal with total power just below the maximum input level to the ADC. In both cases, the spurs at DC, Fs/4 and Fs/2 were removed. The power over the entire Nyquist band (except the noise signal) was integrated and the average number is reported.

6.7 Electrical Characteristics: Analog Input/Output and Reference

TA = 25°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
VIN_FSR Analog Differential Input Full Scale Range NON-EXTENDED CONTROL MODE
FSR Pin Low ADC12D1000
TA = TMIN to TMAX

540
600
660
mVP-P
ADC12D1600
TA = TMIN to TMAX

540
600
660
mVP-P
FSR Pin High ADC12D1000
TA = TMIN to TMAX

740
800
860
mVP-P
ADC12D1600
TA = TMIN to TMAX

740
800
860
mVP-P
EXTENDED CONTROL MODE
FM(14:0) = 0000h 600 mVP-P
FM(14:0) = 4000h (default) 800 mVP-P
FM(14:0) = 7FFFh 1000 mVP-P
CIN Analog Input Capacitance,
Non-DES Mode(1)(2)
Differential 0.02 pF
Each input pin to ground 1.6 pF
Analog Input Capacitance,
DES Mode(1)(2)
Differential 0.08 pF
Each input pin to ground 2.2 pF
RIN Differential Input Resistance ADC12D1000
TA = TMIN to TMAX

91
100
109
Ω
ADC12D1600
TA = TMIN to TMAX

91
100
109
Ω
COMMON-MODE OUTPUT
VCMO Common-Mode Output Voltage ICMO = ±100 µA ADC12D1000
TA = TMIN to TMAX

1.15
1.25
1.35
V
ADC12D1600
TA = TMIN to TMAX

1.15
1.25
1.35
V
TC_VCMO Common-Mode Output Voltage Temperature Coefficient ICMO = ±100 µA 38 ppm/°C
VCMO_LVL VCMO input threshold to set
DC-coupling Mode
0.63 V
CL_VCMO Maximum VCMO Load Capacitance See(1) 80 pF
BANDGAP REFERENCE
VBG Bandgap Reference Output Voltage IBG = ±100 µA ADC12D1000
TA = TMIN to TMAX

1.15
1.25
1.35
V
ADC12D1600
TA = TMIN to TMAX

1.15
1.25
1.35
V
TC_VBG Bandgap Reference Voltage Temperature Coefficient IBG = ±100 µA 32 ppm/°C
CL_VBG Maximum Bandgap Reference load Capacitance See(1) 80 pF
(1) This parameter is specified by design and is not tested in production.
(2) The differential and pin-to-ground input capacitances are lumped capacitance values from design; they are defined as shown belowADC12D1000 ADC12D1600 30091636.gif

6.8 Electrical Characteristics: I-Channel To Q-Channel

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Offset Match 2 LSB
Positive Full-Scale Match Zero offset selected in
Control Register
2 LSB
Negative Full-Scale Match Zero offset selected in
Control Register
2 LSB
Phase Matching (I, Q) fIN = 1 GHz < 1 Degree
X-TALK Crosstalk from I-channel (Aggressor) to Q-channel (Victim) Aggressor = 867 MHz F.S.
Victim = 100 MHz F.S.
−70 dB
Crosstalk from Q-channel (Aggressor) to I-channel (Victim) Aggressor = 867 MHz F.S.
Victim = 100 MHz F.S.
−70 dB

6.9 Electrical Characteristics: Converter and Sampling Clock

TA = 25°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN_CLK Differential Sampling Clock Input Level(2) Sine Wave Clock
Differential Peak-to-Peak
ADC12D1000
TA = TMIN to TMAX

0.4
0.6
2
VP-P
ADC12D1600
TA = TMIN to TMAX

0.4
0.6
2
VP-P
Square Wave Clock
Differential Peak-to-Peak
ADC12D1000
TA = TMIN to TMAX

0.4
0.6
2
VP-P (min)
ADC12D1600
TA = TMIN to TMAX

0.4
0.6
2
VP-P (max)
CIN_CLK Sampling Clock Input Capacitance(1) Differential 0.1 pF
Each input to ground 1 pF
RIN_CLK Sampling Clock Differential Input Resistance 100 Ω

6.10 Electrical Characteristics: Autosync Feature

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN_RCLK Differential RCLK Input Level Differential Peak-to-Peak 360 mVP-P
CIN_RCLK RCLK Input Capacitance Differential 0.1 pF
Each input to ground 1
RIN_RCLK RCLK Differential Input Resistance 100 Ω
IIH_RCLK Input Leakage Current;
VIN = VA
22 µA
IIL_RCLK Input Leakage Current;
VIN = GND
–33 µA
VO_RCOUT Differential RCOut Output Voltage 360 mV

6.11 Electrical Characteristics: Digital Control and Output Pin

TA = 25°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DIGITAL CONTROL PINS (DES, CalDly, CAL, PDI, PDQ, TPM, NDM, FSR, DDRPh, ECE, SCLK, SDI, SCS)
VIH Logic High Input Voltage TA = TMIN to TMAX 0.7×VA V
VIL Logic Low Input Voltage TA = TMIN to TMAX 0.3×VA V
IIH Input Leakage Current;
VIN = VA
0.02 μA
IIL Input Leakage Current;
VIN = GND
FSR, CalDly, CAL, NDM, TPM, DDRPh, DES –0.02 μA
SCS, SCLK, SDI –17 μA
PDI, PDQ, ECE –38 μA
CIN_DIG Digital Control Pin Input Capacitance(1) Measured from each control pin to GND 1.5 pF
DIGITAL OUTPUT PINS (DATA, DCLKI, DCLKQ, ORI, ORQ)
VOD LVDS Differential Output Voltage VBG = Floating, OVS = High ADC12D1000
TA = TMIN to TMAX

400
630
800
mVP-P
ADC12D1600
TA = TMIN to TMAX

400
630
800
mVP-P
VBG = Floating, OVS = Low ADC12D1000
TA = TMIN to TMAX

230
460
630
mVP-P
ADC12D1600
TA = TMIN to TMAX

230
460
630
mVP-P
VBG = VA, OVS = High 670 mVP-P
VBG = VA, OVS = Low 500 mVP-P
ΔVO DIFF Change in LVDS Output Swing Between Logic Levels ±1 mV
VOS Output Offset Voltage VBG = Floating 0.8 V
VBG = VA 1.2 V
ΔVOS Output Offset Voltage Change Between Logic Levels ±1 mV
IOS Output Short-Circuit Current VBG = Floating;
D+ and D− connected to 0.8 V
±4 mA
ZO Differential Output Impedance 100 Ω
VOH Logic High-Output Level CalRun, IOH = −100 µA(2),
SDO, IOH = −400 µA(2)
1.65 V
VOL Logic Low Output Level CalRun, IOL = 100 µA(2),
SDO, IOL = 400 µA(2)
0.15 V
DIFFERENTIAL DCLK RESET PINS (DCLK_RST)
VCMI_DRST DCLK_RST Common-Mode Input Voltage 1.25 V
VID_DRST Differential DCLK_RST Input Voltage VIN_CLK VP-P
RIN_DRST Differential DCLK_RST Input Resistance See(1) 100 Ω

6.12 Electrical Characteristics: Power Supply

TA = 25°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IA Analog Supply Current PDI = PDQ = Low ADC12D1000 1110 mA
ADC12D1600 1235
PDI = Low; PDQ = High ADC12D1000 610 mA
ADC12D1600 670
PDI = High; PDQ = Low ADC12D1000 610 mA
ADC12D1600 670
PDI = PDQ = High 15 mA
ITC Track-and-Hold and Clock Supply Current PDI = PDQ = Low ADC12D1000 400 mA
ADC12D1600 470
PDI = Low; PDQ = High ADC12D1000 240 mA
ADC12D1600 280
PDI = High; PDQ = Low ADC12D1000 240 mA
ADC12D1600 280
PDI = PDQ = High 4 mA
IDR Output Driver Supply Current PDI = PDQ = Low ADC12D1000 305 mA
ADC12D1600 325
PDI = Low; PDQ = High ADC12D1000 160 mA
ADC12D1600 170
PDI = High; PDQ = Low ADC12D1000 160 mA
ADC12D1600 170
PDI = PDQ = High 3 mA
IE Digital Encoder Supply Current PDI = PDQ = Low ADC12D1000 80 mA
ADC12D1600 140
PDI = Low; PDQ = High ADC12D1000 40 mA
ADC12D1600 70
PDI = High; PDQ = Low ADC12D1000 40 mA
ADC12D1600 70
PDI = PDQ = High 1 mA
ITOTAL Total Supply Current 1:2 Demux Mode
PDI = PDQ = Low
ADC12D1000
TA = TMIN to TMAX
1895
2105
mA
ADC12D1600
TA = TMIN to TMAX
2170
2310
Non-Demux Mode
PDI = PDQ = Low
ADC12D1000 1780 mA
ADC12D1600 2040
PC Power Consumption 1:2 Demux Mode
PDI = PDQ = Low ADC12D1000
TA = TMIN to TMAX
3.60
4
W
ADC12D1600
TA = TMIN to TMAX
4.12
4.4
PDI = Low; PDQ = High ADC12D1000 1.99 W
ADC12D1600 2.26
PDI = High; PDQ = Low ADC12D1000 1.99 W
ADC12D1600 2.26
PDI = PDQ = High 43 mW
Non-Demux Mode
PDI = PDQ = Low
ADC12D1000 3.38 W
ADC12D1600 3.88

6.13 Electrical Characteristics: AC

TA = 25°C, unless otherwise noted
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SAMPLING CLOCK (CLK)
fCLK (max) Maximum Sampling Clock Frequency ADC12D1000
TA = TMIN to TMAX
1.0 GHz
ADC12D1600
TA = TMIN to TMAX
1.6
fCLK (min) Minimum Sampling Clock Frequency Non-DES Mode; LFS = 0b ADC12D1000
TA = TMIN to TMAX
300 MHz
ADC12D1600
TA = TMIN to TMAX
300
Non-DES Mode; LFS = 1b, TA = TMIN to TMAX 150 MHz
DES Mode, TA = TMIN to TMAX 500 MHz
Sampling Clock Duty Cycle fCLK(min) ≤ fCLK ≤ fCLK(max)(2) ADC12D1000
TA = TMIN to TMAX

20%
50%
80%
ADC12D1600
TA = TMIN to TMAX

20%
50%
80%
tCL Sampling Clock Low Time See(1) ADC12D1000
TA = TMIN to TMAX

200
500 ps
ADC12D1600
TA = TMIN to TMAX

125
312.5
tCH Sampling Clock High Time See(1) ADC12D1000
TA = TMIN to TMAX

200
500 p
ADC12D1600
TA = TMIN to TMAX

125
312.5
DATA CLOCK (DCLKI, DCLKQ)
DCLK Duty Cycle See(1) ADC12D1000
TA = TMIN to TMAX

45%
50%
55%
ADC12D1600
TA = TMIN to TMAX

45%
50%
55%
tSR Setup Time DCLK_RST± See(2) 45 ps
tHR Hold Time DCLK_RST± See(2) 45 ps
tPWR Pulse Width DCLK_RST± See(1), TA = TMIN to TMAX 5 Sampling Clock Cycles
tSYNC_DLY DCLK Synchronization Delay 90° Mode(1), TA = TMIN to TMAX 4 Sampling Clock Cycles
0° Mode(1), TA = TMIN to TMAX 5
tLHT Differential Low-to-High Transition Time 10%-to-90%, CL = 2.5 pF 200 ps
tHLT Differential High-to-Low Transition Time 10%-to-90%, CL = 2.5 pF 200 ps
tSU Data-to-DCLK Setup Time 90° Mode(1) ADC12D1000 870 ps
ADC12D1600 500
tH DCLK-to-Data Hold Time 90° Mode(1) ADC12D1000 870 ps
ADC12D1600 500
tOSK DCLK-to-Data Output Skew 50% of DCLK transition to 50% of Data transition(1) ±50 ps
DATA INPUT-TO-OUTPUT
tAD Aperture Delay Sampling CLK+ Rise to Acquisition of Data 1.15 ns
tAJ Aperture Jitter 0.2 ps (rms)
tOD Sampling Clock-to Data Output Delay (in addition to Latency) 50% of Sampling Clock transition to 50% of Data transition 3.2 ns
tLAT Latency in 1:2 Demux Non-DES Mode(1) DI, DQ Outputs, TA = TMIN to TMAX 34 Sampling Clock Cycles
DId, DQd Outputs, TA = TMIN to TMAX 35
Latency in 1:4 Demux DES Mode(1) DI Outputs, TA = TMIN to TMAX 34
DQ Outputs, TA = TMIN to TMAX 34.5
DId Outputs, TA = TMIN to TMAX 35
DQd Outputs, TA = TMIN to TMAX 35.5
Latency in Non-Demux Non-DES Mode(1) DI Outputs, TA = TMIN to TMAX 34
DQ Outputs, TA = TMIN to TMAX 34
Latency in Non-Demux DES Mode(1) DI Outputs, TA = TMIN to TMAX 34
DQ Outputs, TA = TMIN to TMAX 34.5
tORR Over-Range Recovery Time Differential VIN step from ±1.2 V to 0 V to accurate conversion 1 Sampling Clock Cycle
tWU Wake-Up Time (PDI/PDQ low to Rated Accuracy Conversion) Non-DES Mode(1) 500 ns
DES Mode(1) 1 µs

6.14 Timing Requirements: Serial Port Interface

TA = 25°C, unless otherwise noted
MIN TYP MAX UNIT
fSCLK Serial Clock Frequency See(1) 15 MHz
Serial Clock Low Time TA = TMIN to TMAX 30 ns
Serial Clock High Time TA = TMIN to TMAX 30 ns
tSSU Serial Data-to-Serial Clock Rising Setup Time See(1) 2.5 ns
tSH Serial Data-to-Serial Clock Rising Hold Time See(1) 1 ns
tSCS SCS-to-Serial Clock Rising Setup Time 2.5 ns
tHCS SCS-to-Serial Clock Falling Hold Time 1.5 ns
tBSU Bus turnaround time 10 ns

6.15 Timing Requirements: Calibration

TA = 25°C, unless otherwise noted
MIN TYP MAX UNIT
tCAL Calibration Cycle Time CSS = 0b 5.2·107 Sampling Clock Cycles
CSS = 1b
tCAL_L CAL Pin Low Time See(1), TA = TMIN to TMAX 1280 Sampling Clock Cycles
tCAL_H CAL Pin High Time See(1), TA = TMIN to TMAX 1280
tCalDly Calibration delay determined by CalDly Pin(1) CalDly = Low, TA = TMIN to TMAX 224 Sampling Clock Cycles
CalDly = High, TA = TMIN to TMAX 230
(1) This parameter is specified by design and is not tested in production.
(2) This parameter is specified by design and/or characterization and is not tested in production.
(3) Proper common mode voltage must be maintained to ensure proper output codes, especially during input overdrive.
ADC12D1000 ADC12D1600 30091659.gif
The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.
Figure 1. Clocking in 1:2 Demux Non-DES Mode*
ADC12D1000 ADC12D1600 30091660.gif
The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.
Figure 2. Clocking in Non-Demux Non-DES Mode*
ADC12D1000 ADC12D1600 30091699.gif
The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.
Figure 3. Clocking in 1:4 Demux DES Mode*
ADC12D1000 ADC12D1600 30091696.gif
The timing for these figures is shown for the one input only (I or Q). However, both I- and Q-inputs may be used. For this case, the I-channel functions precisely the same as the Q-channel, with VinI, DCLKI, DId and DI instead of VinQ, DCLKQ, DQd and DQ. Both I- and Q-channel use the same CLK.
Figure 4. Clocking in Non-Demux Mode DES Mode*
ADC12D1000 ADC12D1600 30091620.gifFigure 5. Data Clock Reset Timing (Demux Mode)
ADC12D1000 ADC12D1600 30091625.gifFigure 6. Power-on and On-Command Calibration Timing
ADC12D1000 ADC12D1600 30091619.gifFigure 7. Serial Interface Timing
ADC12D1000 ADC12D1600 30091622.gifFigure 8. Input / Output Transfer Characteristic

6.16 Typical Characteristics

VA = VDR = VTC = VE = 1.9 V, fCLK = 1.0/1.6 GHz, fIN = 498 MHz, TA= 25°C, I-channel, 1:2 Demux Non-DES Mode (1:1 Demux Non-DES Mode has similar performance), unless otherwise stated. For NPR plots, notch width = 25 MHz, fc = 320 MHz.
ADC12D1000 ADC12D1600 30091638.gif
Figure 9. INL vs Code (ADC12D1000)
ADC12D1000 ADC12D1600 30091640.gif
Figure 11. INL vs Temperature (ADC12D1000)
ADC12D1000 ADC12D1600 30091639.gif
Figure 13. DNL vs Code (ADC12D1000)
ADC12D1000 ADC12D1600 30091641.gif
Figure 15. DNL vs Temperature (ADC12D1000)
ADC12D1000 ADC12D1600 30091676.gif
Figure 17. ENOB vs Temperature (ADC12D1000)
ADC12D1000 ADC12D1600 30091677.gif
Figure 19. ENOB vs Supply Voltage (ADC12D1000)
ADC12D1000 ADC12D1600 30091678.gif
Figure 21. ENOB vs Clock Frequency (ADC12D1000)
ADC12D1000 ADC12D1600 30091679.gif
Figure 23. ENOB vs Input Frequency (ADC12D1000)
ADC12D1000 ADC12D1600 30091642.gif
Figure 25. ENOB vs VCMI (ADC12D1000)
ADC12D1000 ADC12D1600 30091668.gif
Figure 27. SNR vs Temperature (ADC12D1000)
ADC12D1000 ADC12D1600 30091669.gif
Figure 29. SNR vs Supply Voltage (ADC12D1000)
ADC12D1000 ADC12D1600 30091670.gif
Figure 31. SNR vs Clock Frequency (ADC12D1000)
ADC12D1000 ADC12D1600 30091671.gif
Figure 33. SNR vs Input Frequency (ADC12D1000)
ADC12D1000 ADC12D1600 30091672.gif
Figure 35. THD vs Temperature (ADC12D1000)
ADC12D1000 ADC12D1600 30091673.gif
Figure 37. THD vs Supply Voltage (ADC12D1000)
ADC12D1000 ADC12D1600 30091674.gif
Figure 39. THD vs Clock Frequency (ADC12D1000)
ADC12D1000 ADC12D1600 30091675.gif
Figure 41. THD vs Input Frequency (ADC12D1000)
ADC12D1000 ADC12D1600 30091685.gif
Figure 43. SFDR vs Temperature (ADC12D1000)
ADC12D1000 ADC12D1600 30091684.gif
Figure 45. SFDR vs Supply Voltage (ADC12D1000)
ADC12D1000 ADC12D1600 30091682.gif
Figure 47. SFDR vs Clock Frequency (ADC12D1000)
ADC12D1000 ADC12D1600 30091683.gif
Figure 49. SFDR vs Input Frequency (ADC12D1000)
ADC12D1000 ADC12D1600 30091687.gif
Figure 51. Spectral Response at FIN = 498 MHz (ADC12D1000)
ADC12D1000 ADC12D1600 30091688.gif
Figure 53. Spectral Response at FIN = 498 MHz (ADC12D1000)
ADC12D1000 ADC12D1600 30091663.gif
Figure 55. Crosstalk vs Source Frequency (ADC12D1000)
ADC12D1000 ADC12D1600 30091648.gif
Figure 57. Full Power Bandwidth (ADC12D1000)
ADC12D1000 ADC12D1600 30091681.gif
Figure 59. Power Consumption vs Clock Frequency (ADC12D1000)
ADC12D1000 ADC12D1600 30091631.gif
Figure 61. NPR vs RMS Noise Loading Level (ADC12D1000)
ADC12D1000 ADC12D1600 30091649.gif
Figure 10. INL vs Code (ADC12D1600)
ADC12D1000 ADC12D1600 30091650.gif
Figure 12. INL vs Temperature (ADC12D1600)
ADC12D1000 ADC12D1600 30091651.gif
Figure 14. DNL vs Code (ADC12D1600)
ADC12D1000 ADC12D1600 30091652.gif
Figure 16. DNL vs Temperature (ADC12D1600)
ADC12D1000 ADC12D1600 30091654.gif
Figure 18. ENOB vs Temperature (ADC12D1600)
ADC12D1000 ADC12D1600 30091655.gif
Figure 20. ENOB vs Supply Voltage (ADC12D1600)
ADC12D1000 ADC12D1600 30091656.gif
Figure 22. ENOB vs Clock Frequency (ADC12D1600)
ADC12D1000 ADC12D1600 30091657.gif
Figure 24. ENOB vs Input Frequency (ADC12D1600)
ADC12D1000 ADC12D1600 30091658.gif
Figure 26. ENOB vs VCMI (ADC12D1600)
ADC12D1000 ADC12D1600 30091614.gif
Figure 28. SNR vs Temperature (ADC12D1600)
ADC12D1000 ADC12D1600 30091615.gif
Figure 30. SNR vs Supply Voltage (ADC12D1600)
ADC12D1000 ADC12D1600 30091616.gif
Figure 32. SNR vs Clock Frequency (ADC12D1600)
ADC12D1000 ADC12D1600 30091617.gif
Figure 34. SNR vs Input Frequency (ADC12D1600)
ADC12D1000 ADC12D1600 30091618.gif
Figure 36. THD vs Temperature (ADC12D1600)
ADC12D1000 ADC12D1600 30091621.gif
Figure 38. THD vs Supply Voltage (ADC12D1600)
ADC12D1000 ADC12D1600 30091695.gif
Figure 40. THD vs Clock Frequency (ADC12D1600)
ADC12D1000 ADC12D1600 30091623.gif
Figure 42. THD vs Input Frequency (ADC12D1600)
ADC12D1000 ADC12D1600 30091624.gif
Figure 44. SFDR vs Temperature (ADC12D1600)
ADC12D1000 ADC12D1600 30091628.gif
Figure 46. SFDR vs Supply Voltage (ADC12D1600)
ADC12D1000 ADC12D1600 30091661.gif
Figure 48. SFDR vs Clock Frequency (ADC12D1600)
ADC12D1000 ADC12D1600 30091662.gif
Figure 50. SFDR vs Input Frequency (ADC12D1600)
ADC12D1000 ADC12D1600 30091667.gif
Figure 52. Spectral Response at FIN = 498 MHz (ADC12D1600)
ADC12D1000 ADC12D1600 30091686.gif
Figure 54. Spectral Response at FIN = 498 MHz (ADC12D1600)
ADC12D1000 ADC12D1600 30091633.gif
Figure 56. Crosstalk vs Source Frequency (ADC12D1600)
ADC12D1000 ADC12D1600 30091689.gif
Figure 58. Full Power Bandwidth (ADC12D1600)
ADC12D1000 ADC12D1600 30091691.gif
Figure 60. Power Consumption vs Clock Frequency (ADC12D1600)
ADC12D1000 ADC12D1600 30091632.gif
Figure 62. NPR vs RMS Noise Loading Level (ADC12D1600)