JAJSSY9 February   2024 ADC12DL1500 , ADC12DL2500 , ADC12DL500

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Pin Configuration and Functions
  6. Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics: DC Specifications
    6. 5.6  Electrical Characteristics: Power Consumption
    7. 5.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 5.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 5.9  Timing Requirements
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagrams
    12. 5.12 Typical Characteristics - ADC12DL500
    13. 5.13 Typical Characteristics - ADC12DL1500 (1GSPS)
    14. 5.14 Typical Characteristics - ADC12DL1500 (1.5GSPS)
    15. 5.15 Typical Characteristics - ADC12DL2500 (2GSPS)
    16. 5.16 Typical Characteristics - ADC12DL2500 (2.5GSPS)
  7. Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Analog Input Protection
        2. 6.3.1.2 Full-Scale Voltage (VFS) Adjustment
        3. 6.3.1.3 Analog Input Offset Adjust
      2. 6.3.2 ADC Core
        1. 6.3.2.1 ADC Theory of Operation
        2. 6.3.2.2 ADC Core Calibration
        3. 6.3.2.3 ADC Overrange Detection
        4. 6.3.2.4 Code Error Rate (CER)
        5. 6.3.2.5 Internal Dither
      3. 6.3.3 Timestamp
      4. 6.3.4 Clocking
        1. 6.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 6.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 6.3.4.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 6.3.4.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 6.3.4.3.2 Automatic SYSREF Calibration
      5. 6.3.5 LVDS Digital Interface
        1. 6.3.5.1 Multi-Device Synchronization and Deterministic Latency Using Strobes
          1. 6.3.5.1.1 Dedicated Strobe Pins
          2. 6.3.5.1.2 Reduced Width Interface With Dedicated Strobe Pins
          3. 6.3.5.1.3 LSB Replacement With a Strobe
          4. 6.3.5.1.4 Strobe Over All Data Pairs
      6. 6.3.6 Alarm Monitoring
        1. 6.3.6.1 Clock Upset Detection
      7. 6.3.7 Temperature Monitoring Diode
      8. 6.3.8 Analog Reference Voltage
    4. 6.4 Device Functional Modes
      1. 6.4.1 Dual-Channel Mode (Non-DES Mode)
      2. 6.4.2 Internal Dither Modes
      3. 6.4.3 Single-Channel Mode (DES Mode)
      4. 6.4.4 LVDS Output Driver Modes
      5. 6.4.5 LVDS Output Modes
        1. 6.4.5.1 Staggered Output Mode
        2. 6.4.5.2 Aligned Output Mode
        3. 6.4.5.3 Reducing the Number of Strobes
        4. 6.4.5.4 Reducing the Number of Data Clocks
        5. 6.4.5.5 Scrambling
        6. 6.4.5.6 Digital Interface Test Patterns and LVSD SYNC Functionality
          1. 6.4.5.6.1 Active Pattern
          2. 6.4.5.6.2 Synchronization Pattern
          3. 6.4.5.6.3 User-Defined Test Pattern
      6. 6.4.6 Power-Down Modes
      7. 6.4.7 Calibration Modes and Trimming
        1. 6.4.7.1 Foreground Calibration Mode
      8. 6.4.8 Offset Calibration
      9. 6.4.9 Trimming
    5. 6.5 Programming
      1. 6.5.1 Using the Serial Interface
        1. 6.5.1.1 SCS
        2. 6.5.1.2 SCLK
        3. 6.5.1.3 SDI
        4. 6.5.1.4 SDO
        5. 6.5.1.5 80
        6. 6.5.1.6 Streaming Mode
        7. 6.5.1.7 82
  8. Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Applications
      1. 7.2.1 Reconfigurable Dual-Channel 2.5GSPS or Single-Channel 5GSPS Oscilloscope
        1. 7.2.1.1 Design Requirements
          1. 7.2.1.1.1 Input Signal Path
          2. 7.2.1.1.2 Clocking
          3. 7.2.1.1.3 ADC12DLx500
        2. 7.2.1.2 Application Curves
    3. 7.3 Initialization Set Up
    4. 7.4 Power Supply Recommendations
      1. 7.4.1 Power Sequencing
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  9. Register Maps
    1. 8.1 SPI_REGISTER_MAP Registers
  10. Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Layout Guidelines

There are many critical signals that require specific care during board design:

  1. Analog input signals
  2. CLK and SYSREF
  3. LVDS data outputs at up to 1.6Gbps
  4. Power connections
  5. Ground connections

Items 1 and 2 must be routed for excellent signal quality at high frequencies. Use the following general practices for these signals:

  1. Route using loosely coupled 100Ω differential traces. This routing minimizes impact of corners and length-matching serpentine on pair impedance.
  2. Provide adequate pair-to-pair spacing to minimize crosstalk.
  3. Provide adequate ground plane pour spacing to minimize coupling with the high-speed traces.
  4. Use smoothly radiused corners. Avoid 45- or 90-degree bends.
  5. Incorporate ground plane cutouts at component landing pads to avoid impedance discontinuities at these locations. Cutout below the landing pads on one or multiple ground planes to achieve a pad size or stackup height that achieves the needed 50-Ω, single-ended impedance.
  6. Avoid routing traces near irregularities in the reference ground planes. Irregularities include ground plane clearances associated with power and signal vias and through-hole component leads.
  7. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias.
  8. When high-speed signals must transition to another layer using vias, transition as far through the board as possible (top to bottom is best case) to minimize via stubs on top or bottom of the vias. If layer selection is not flexible, use back-drilled or buried, blind vias to eliminate stubs.

The LVDS data outputs must be routed with sufficient signal quality using the following general practices:

  1. Route using tightly coupled 100Ω differential traces to minimize the routing area and decrease crosstalk between adjacent data pairs.
  2. Use smoothly radiused corners or 45-degree bends. Avoid 90-degree bends.
  3. Avoid routing traces near irregularities in the reference ground planes. Irregularities include ground plane clearances associated with power and signal vias and through-hole component leads.
  4. Provide symmetrically located ground tie vias adjacent to any high-speed signal vias.
  5. Data, clock, and strobe pairs must be sufficiently delay matched to provide adequate timing margin at the receiver. If routing on multiple layers, trace lengths must be compensated for the delay mismatch introduced by the effective dielectric constant of each layer.

In addition, TI recommends performing signal quality simulations of the critical signal traces before committing to fabrication. Perform insertion loss, return loss, and time domain reflectometry (TDR) evaluations.

The power and ground connections for the device are also very important. These rules must be followed:

  1. Provide low-resistance connection paths to all power and ground pins.
  2. Use multiple power layers if necessary to access all pins.
  3. Avoid narrow isolated paths that increase connection resistance.
  4. Use a signal, ground, or power circuit board stackup to maximum coupling between the ground and power planes.