JAJSOU1B データシート

JAJSOU1B june 2022 – august 2023 ADC32RF54 , ADC32RF55

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RTD|64
- MPQF141C

サーマルパッド・メカニカル・データ

RTD|64
- QFND625

発注情報

jajsou1b_oa

7.3.3.1 SYSREF Capture Detection

The SYSREF input signal rising edge should be edge aligned with the rising edge of the sampling clock in order to maximize the setup and hold times. The ADC32RF5x includes an internal SYSREF monitoring circuitry to detect possible metastability resulting in a clock cycle slip; and thus, misalignment across devices.

The sampling clock gets delayed by ~160 ps and then captures the SYSREF signal. The SYSREF monitoring circuitry captures the SYSREF signal ±50 ps (-50, -25, +16, +32, +48 ps) around the main SYSREF capture. In ideal conditions no SYSREF transition happens within the 100 ps SYSREF capture window and all XOR flags show "0". If a SYSREF/clock misalignment happens and the SYSREF transition falls within the SYSREF monitoring window, then one of the XOR flags (which monitor adjacent SYSREF captures within the window) shows a "1" and the SYSREF can be adjusted externally.

The SYSREF monitor registers are not sticky registers, which are updated at every rising edge of SYSREF.

Figure 7-16 SYSREF Detection Circuitry

Figure 7-17 shows a misaligned SYSREF signal where the SYSREF signal arrives much later than the sampling clock rising edge. The SYSREF window feature checks if the SYSREF transition is within ±50 ps of the instant when the SYSREF signal gets captured by the sampling clock.

In this example, the delayed SYSREF signal transitions between the "B" and "C" flip flop which raises the XOR2 flag. The XOR flags get reported in register 0x22F in the digital page. In this exampe, Register 0x22F reads back 0x8B, as shown in Table 7-11.

Figure 7-17 Detection of SYSREF Transition Within Capture Window

Table 7-11 SYSREF Window Register Example (0x22F)

ADDR	D7	D6	D5	D4	D3	D2	D1	D0
0x22F	1	SYSREF X5	SYSREF X4	SYSREF X3	SYSREF X2	SYSREF X1	SYSREF OR	1
0x22F	1	0	0	0	1	0	1	1