JAJSLC0 March   2024 ADC3683-SP

PRODMIX  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics - Power Consumption
    6. 5.6 Electrical Characteristics - DC Specifications
    7. 5.7 Electrical Characteristics - AC Specifications
    8. 5.8 Timing Requirements
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
        1. 7.3.1.1 Analog Front End Design
          1. 7.3.1.1.1 Sampling Glitch Filter Design
          2. 7.3.1.1.2 Analog Input Termination and DC Bias
            1. 7.3.1.1.2.1 AC-Coupling
            2. 7.3.1.1.2.2 DC-Coupling
        2. 7.3.1.2 Auto-Zero Feature
      2. 7.3.2 Clock Input
        1. 7.3.2.1 Single Ended vs Differential Clock Input
        2. 7.3.2.2 Signal Acquisition Time Adjust
      3. 7.3.3 Voltage Reference
        1. 7.3.3.1 Internal Voltage Reference
        2. 7.3.3.2 External Voltage Reference (VREF)
        3. 7.3.3.3 External Voltage Reference with Internal Buffer (REFBUF)
      4. 7.3.4 Digital Down Converter
        1. 7.3.4.1 DDC MUX
        2. 7.3.4.2 Digital Filter Operation
        3. 7.3.4.3 FS/4 Mixing with Real Output
        4. 7.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 7.3.4.5 Decimation Filter
        6. 7.3.4.6 SYNC
        7. 7.3.4.7 Output Formatting with Decimation
      5. 7.3.5 Digital Interface
        1. 7.3.5.1 Output Formatter
        2. 7.3.5.2 Output Scrambler
        3. 7.3.5.3 Output Bit Mapper
          1. 7.3.5.3.1 2-Wire Mode
          2. 7.3.5.3.2 1-Wire Mode
          3. 7.3.5.3.3 ½-Wire Mode
        4. 7.3.5.4 Output Interface or Mode Configuration
          1. 7.3.5.4.1 Configuration Example
        5. 7.3.5.5 Output Data Format
      6. 7.3.6 Test Pattern
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Power Down Options
      3. 7.4.3 Digital Channel Averaging
    5. 7.5 Programming
      1. 7.5.1 Configuration using PINs only
      2. 7.5.2 Configuration using the SPI interface
        1. 7.5.2.1 Register Write
        2. 7.5.2.2 Register Read
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Signal Path
        2. 8.2.2.2 Sampling Clock
        3. 8.2.2.3 Voltage Reference
      3. 8.2.3 Application Curves
    3. 8.3 Initialization Set Up
      1. 8.3.1 Register Initialization During Operation
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Register Map
    1. 9.1 Detailed Register Description
  11. 10Device and Documentation Support
    1. 10.1 ドキュメントの更新通知を受け取る方法
    2. 10.2 サポート・リソース
    3. 10.3 Trademarks
    4. 10.4 静電気放電に関する注意事項
    5. 10.5 用語集
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
  • HBP|64
サーマルパッド・メカニカル・データ
発注情報

5.8 Timing Requirements

Typical values are at TA = 25°C, MIN and MAX timing values are characterized over the full temperature range TMIN = –55°C to TMAX = 105°C and are NOT production tested, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, 1.6 V external reference, and –1-dBFS differential input, unless otherwise noted
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
ADC Timing Specifications
tAD Aperture Delay 0.85 ns
tA Aperture Jitter Square wave clock with fast edges 180 fs
tJ Jitter on DCLKIN ± 50 (1) ps
tACQ Signal acquisition period, referenced to sampling clock falling edge FS = 10 Msps -TS/2 Sampling Clock Period
FS = 25 Msps -TS/2
FS = 65 Msps -TS/4
tCONV Signal conversion period, referenced to sampling clock falling edge FS = 10 Msps +TS × 1/5 Sampling Clock Period
FS = 25 Msps +TS × 3/8
FS = 65 Msps +TS × 5/8
Wake up time Time to valid data after coming out of power down. Internal reference. Bandgap reference enabled, single ended clock us
Bandgap reference enabled, differential clock
Bandgap reference disabled, single ended clock ms
Bandgap reference disabled, differential clock
Time to valid data after coming out of power down.
External 1.6V reference.		 Bandgap reference enabled, single ended clock us
Bandgap reference enabled, differential clock 100
Bandgap reference disabled, single ended clock ms
Bandgap reference disabled, differential clock
tS,SYNC Setup time for SYNC input signal Referenced to sampling clock rising edge 500 ps
tH,SYNC Hold time for SYNC input signal 600
ADC Latency Signal input to data output SLVDS 2-wire 2 ADC clock cycles
SLVDS 1-wire 1
SLVDS 1/2-wire 1
Add Latency Real decimation by 2 21   Output clock cycles
Complex decimation by 2   22  
Real or complex decimation by 4, 8, 16, 32   23  
Interface Timing: Serial LVDS Interface
tPD Propagation delay: sampling clock falling edge to DCLK rising edge Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 + TDCLK + tCDCLK 3 + TDCLK + tCDCLK 4 + TDCLK + tCDCLK ns
Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns.
TDCLK = DCLK period
tCDCLK = Sampling clock falling edge to DCLKIN falling edge		 2 + tCDCLK 3 + tCDCLK 4 + tCDCLK ns
tCD DCLK rising edge to output data delay,
2-wire SLVDS		 Fout = 10 MSPS, DA/B0,1 = 90 MBPS 0 0.1 ns
Fout = 65 MSPS, DA/B0,1 = 585 MBPS 0 0.1
DCLK rising edge to output data delay,
1-wire SLVDS		 Fout = 10 MSPS, DA/B0 = 180 MBPS 0.1 0.2
Fout = 55 MSPS, DA/B0 = 990 MBPS -0.4 0.1
DCLK rising edge to output data delay,
1/2-wire SLVDS		 Fout = 5 MSPS, DA0 = 180 MBPS 0 0.1
Fout = 25 MSPS, DA0 = 720 MBPS 0 0.1
tDV Data valid, 2-wire SLVDS Fout = 10 MSPS, DA/B0,1 = 90 MBPS 10.5 10.7 ns
Fout = 65 MSPS, DA/B0,1 = 585 MBPS 1.3 1.4
Data valid, 1-wire SLVDS Fout = 10 MSPS, DA/B0 = 180 MBPS 4.7 4.8
Fout = 55 MSPS, DA/B0 = 990 MBPS 0.5 0.6
Data valid, 1/2-wire SLVDS Fout = 5 MSPS, DA0 = 180 MBPS 4.7 4.8
Fout = 25 MSPS, DA0 = 900 MBPS 0.6 0.7
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
fCLK(SCLK) Serial clock frequency 20 MHz
tSU(SEN) SEN to rising edge of SCLK 10 ns
tH(SEN) SEN from rising edge of SCLK 17 ns
tSU(SDIO) SDIO to rising edge of SCLK 17 ns
tH(SDIO) SDIO from rising edge of SCLK 10 ns
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t(OZD) SDIO output to driven 19 ns
t(ODZ) SDIO data to output 17 ns
t(OD) SDIO valid from falling edge of SCLK 19 ns
(1) Max value allowed and does not scale with sample rates.