JAJSIN4D October   2003  – February 2020 ADS1204

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     機能ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements: 5.0 V
    7. 6.7 Timing Requirements: 3.0 V
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Stage
        1. 7.3.1.1 Analog Input
        2. 7.3.1.2 Modulator
      2. 7.3.2 Digital Output
      3. 7.3.3 Equivalent Input Circuits
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Filter Usage
  9. 9 Power Supply Recommendations
    1. 9.1 Power-Supply Sequencing
    2. 9.2 Power-Supply Decoupling
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントの更新通知を受け取る方法
    2. 11.2 サポート・リソース
    3. 11.3 商標
    4. 11.4 静電気放電に関する注意事項
    5. 11.5 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics

over recommended operating free-air temperature range at –40°C to +105°C, AVDD = 5 V, BVDD = 3 V, CH x+ = 0.5 V to 4.5 V, CH x– = 2.5 V, REFIN = REFOUT = internal 2.5 V, CLKIN = 20 MHz, and 16-bit sinc3 filter with decimation by 256 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP(1) MAX UNIT
RESOLUTION
Resolution 16 Bits
DC ACCURACY
INL Integral linearity error(2) ±1 ±3 LSB
±0.001 ±0.005 % FSR
Integral linearity match ±6 LSB
±0.009 % FSR
DNL Differential nonlinearity(3) ±1 LSB
VOS Input offset error –1.4 ±3 mV
Input offset error match ±2 mV
TCVOS Input offset error drift ±2 ±8 µV/°C
GERR Gain error(4) Referenced to VREF ±0.08 ±0.5 % FSR
Gain error match ±0.185 ±0.5 % FSR
TCGERR Gain error drift ±2 ppm/°C
PSRR Power-supply rejection ratio 4.75 V < AVDD < 5.25 V 78 dB
ANALOG INPUT
FSR Full-scale differential range (CH x+) – (CH x–); CH x– = 2.5 V ±2.5 V
Specified differential range (CH x+) – (CH x–); CH x– = 2.5 V ±2 V
Maximum operating input range(3) 0 AVDD V
Input capacitance Common-mode 1.5 pF
Input leakage current CLK turned off ±1 nA
Differential input resistance 100 kΩ
Differential input capacitance 2.5 pF
CMRR Common-mode rejection ratio At DC 100 dB
VIN = ±1.25 VPP at 40 kHz 110
BW Bandwidth FS sine wave, –3 dB 50 MHz
SAMPLING DYNAMICS
Internal clock frequency CLKSEL = 1 8 10 12 MHz
CLKIN External clock frequency CLKSEL = 0 1 20 32 MHz
AC ACCURACY
THD Total harmonic distortion VIN = ±2 VPP at 5 kHz;
–40°C ≤ TA ≤ +85°C		 –96 –88 dB
VIN = ±2 VPP at 5 kHz;
–40°C ≤ TA ≤ +105°C		 –96 –87
SFDR Spurious-free dynamic range VIN = ±2 VPP at 5 kHz 92 100 dB
SNR Signal-to-noise ratio VIN = ±2 VPP at 5 kHz 86 89 dB
SINAD Signal-to-noise + distortion VIN = ±2 VPP at 5 kHz 85 89 dB
Channel-to-channel isolation(3) VIN = ±2 VPP at 50 kHz 85 dB
ENOB Effective number of bits 14 14.5 Bits
VOLTAGE REFERENCE OUTPUT
VOUT Reference voltage output 2.450 2.5 2.550 V
dVOUT/dT Output voltage temperature drift ±20 ppm/°C
Output voltage noise f = 0.1 Hz to 10 Hz, CL = 10 µF 10 µVrms
f = 10 Hz to 10 kHz, CL = 10 µF 12
PSRR Power-supply rejection ratio 60 dB
IOUT Output current 10 µA
ISC Short-circuit current 0.5 mA
Turn-on settling time To 0.1% at CL = 0 100 µs
VOLTAGE REFERENCE INPUT
VIN Reference voltage input 0.5 2.5 2.6 V
Reference input resistance 100 MΩ
Reference input capacitance 5 pF
Reference input current 1 µA
DIGITAL INPUTS(5)
Logic family CMOS with Schmitt Trigger
VIH High-level input voltage 0.7 × BVDD BVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × BVDD V
IIN Input current VI = BVDD or GND ±50 nA
CI Input capacitance 5 pF
DIGITAL OUTPUTS(5)
Logic family CMOS
VOH High-level output voltage BVDD = 4.5 V, IOH = –100 µA 4.44 V
VOL Low-level output voltage BVDD = 4.5 V, IOL = 100 µA 0.5 V
CO Output capacitance 5 pF
CL Load capacitance 30 pF
Data format Bit stream
DIGITAL INPUTS(6)
Logic family LVCMOS
VIH High-level input voltage BVDD = 3.6 V 2 BVDD + 0.3 V
VIL Low-level input voltage BVDD = 2.7 V –0.3 0.8 V
IIN Input current VI = BVDD or GND ±50 nA
CI Input capacitance 5 pF
DIGITAL OUTPUTS(6)
Logic family LVCMOS
VOH High-level output voltage BVDD = 2.7V, IOH = –100 µA BVDD – 0.2 V
VOL Low-level output voltage BVDD = 2.7 V, IOL = 100 µA 0.2 V
CO Output capacitance 5 pF
CL Load capacitance 30 pF
Data format Bit stream
POWER SUPPLY
AVDD Analog supply voltage 4.5 5.5 V
BVDD Buffer I/O supply voltage Low-voltage levels 2.7 3.6 V
5-V logic levels 4.5 5.5
AIDD Analog operating supply current CLKSEL = 1 22.5 30 mA
CLKSEL = 0 22.4 29
BIDD Buffer I/O operating supply current BVDD = 3 V, CLKOUT = 10 MHz 4 mA
BVDD = 5 V, CLKOUT = 10 MHz 4
Power dissipation CLKSEL = 0 122 145 mW
CLKSEL = 1 112.5 150
(1) All typical values are at TA = +25°C.
(2) Integral nonlinearity is defined as the maximum deviation of the line through the end points of the specified input range of the transfer curve for CH x+ = –2 V to +2 V at 2.5 V, expressed either as the number of LSBs or as a percent of measured input range (4 V).
(3) Specified by design.
(4) Maximum values, including temperature drift, are specified over the full specified temperature range.
(5) Applicable for 5.0-V nominal supply: BVDD (min) = 4.5 V and BVDD (max) = 5.5 V.
(6) Applicable for 3.0-V nominal supply: BVDD (min) = 2.7 V and BVDD (max) = 3.6 V.