JAJS168G June   2005  – January 2021 ADS1232 , ADS1234

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Noise Performance
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Analog Inputs (AINPX, AINNX)
      2. 8.3.2  Temperature Sensor (ADS1232 Only)
      3. 8.3.3  Low-Noise PGA
        1. 8.3.3.1 PGA Bypass Capacitor
      4. 8.3.4  Voltage Reference Inputs (REFP, REFN)
      5. 8.3.5  Clock Sources
      6. 8.3.6  Digital Filter Frequency Response
      7. 8.3.7  Settling Time
      8. 8.3.8  Data Rate
      9. 8.3.9  Data Format
      10. 8.3.10 Data Ready and Data Output (DRDY/DOUT)
      11. 8.3.11 Serial Clock Input (SCLK)
      12. 8.3.12 Data Retrieval
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Standby Mode With Offset-Calibration
      4. 8.4.4 Power-Down Mode
      5. 8.4.5 Power-Up Sequence
      6. 8.4.6 Summary of Serial Interface Waveforms
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Decoupling
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 ドキュメントの更新通知を受け取る方法
    2. 12.2 サポート・リソース
    3. 12.3 Trademarks
    4. 12.4 静電気放電に関する注意事項
    5. 12.5 用語集
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Typical Application

Figure 9-1 shows a circuit diagram of the ADS1232 as part of a weigh scale system. In this setup, the ADS1232 is configured to channel 1 input, gain = 128, and 10 SPS data rate. Gain = 128 is selected by tying the GAIN[1:0] pins to logic high (3 V in this example). Input channel 1 and data rate = 10 SPS are selected by tying input channel select pins A0 and TEMP to ground, and by tying the data rate select pin SPEED to ground. The unused channel 2 inputs are tied to ground.

The internal oscillator is selected by grounding the CLKIN/XTAL1 pin. The other clock options are 1) 4.9152-MHz crystal across the CLKIN/XTAL1 and XTAL2 pins, or 2) apply a clock to the CLKIN/XTAL1 pin (pin XTAL2 unconnected). The PWDN pin of the ADC is routed to the controller because this pin must be toggled after the ADC is powered. The bridge excitation voltage is connected to the ADC reference input pins (REFP, REFN). Not shown in Figure 9-1 are R-C input filters for the signal and reference inputs. If these filters are used, match the filter time constants to maintain cancellation of noise common to both signal and reference inputs.

GUID-59EF2B1A-3A8D-4372-993C-6F97CC6CD5AE-low.gifFigure 9-1 Weigh-Scale Application