SLVSKW2
January 2026
ADS1278QML-SP
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Pin Configuration and Functions
5
Specifications
5.1
Absolute Maximum Ratings
5.2
ESD Ratings
5.3
Recommended Operating Conditions
5.4
Thermal Information
5.5
Electrical Characteristics
5.6
Quality Conformance Inspection
5.7
Timing Requirements: SPI Format
5.8
Timing Requirements: Frame-Sync Format
5.9
Typical Characteristics
6
Detailed Description
6.1
Overview
6.2
Functional Block Diagram
6.3
Feature Description
6.3.1
Sampling Aperture Matching
6.3.2
Frequency Response
6.3.2.1
High-Speed, Low-Power, And Low-Speed Modes
6.3.2.2
High-Resolution Mode
6.3.3
Phase Response
6.3.4
Settling Time
6.3.5
Data Format
6.3.6
Analog Inputs (AINP, AINN)
6.3.7
Voltage Reference Inputs (VREFP, VREFN)
6.3.8
Clock Input (CLK)
6.3.9
Mode Selection (MODE)
6.3.10
Synchronization (SYNC)
6.3.11
Power-Down ( PWDN)
6.3.12
Format[2:0]
6.3.13
Serial Interface Protocols
6.3.14
SPI Serial Interface
6.3.14.1
SCLK
6.3.14.2
DRDY/FSYNC (SPI Format)
6.3.14.3
DOUT
6.3.14.4
DIN
6.3.15
Frame-Sync Serial Interface
6.3.15.1
SCLK
6.3.15.2
DRDY/FSYNC (Frame-Sync Format)
6.3.15.3
DOUT
6.3.15.4
DIN
6.3.16
DOUT Modes
6.3.16.1
TDM Mode
6.3.16.2
TDM Mode, Fixed-Position Data
6.3.16.3
TDM Mode, Dynamic Position Data
6.3.16.4
Discrete Data Output Mode
6.3.17
Daisy-Chaining
6.3.18
Modulator Output
6.3.19
Pin Test Using Test[1:0] Inputs
6.3.20
VCOM Output
6.4
Device Functional Modes
7
Application and Implementation
7.1
Application Information
7.2
Typical Application
7.2.1
Design Requirements
7.2.2
Detailed Design Procedure
7.2.3
Application Curve
7.3
Power Supply Recommendations
7.4
Layout
7.4.1
Layout Guidelines
7.4.2
Layout Example
8
Device and Documentation Support
8.1
Receiving Notification of Documentation Updates
8.2
Community Resources
8.3
Trademarks
9
Revision History
10
Mechanical, Packaging, and Orderable Information
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Data Sheet
ADS1278QML-SP
Radiation Hardened 8-Ch Simultaneous-Sampling
24-Bit Analog-to-Digital Converter