SBAS486F November   2009  – February 2016 ADS41B29 , ADS41B49

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: General
    6. 6.6  Electrical Characteristics: ADS41B29, ADS41B49
    7. 6.7  Digital Characteristics
    8. 6.8  Timing Requirements: LVDS and CMOS Modes
    9. 6.9  Timing Requirements: Reset
    10. 6.10 Timing Requirements: LVDS Timing Across Sampling Frequencies
    11. 6.11 Timing Requirements: CMOS Timing Across Sampling Frequencies
    12. 6.12 Timing Requirements: CMOS Timing Across Sampling Frequencies
    13. 6.13 Typical Characteristics: ADS41B49
    14. 6.14 Typical Characteristics: ADS41B29
    15. 6.15 Typical Characteristics: General
    16. 6.16 Typical Characteristics: Contour
  7. Parameter Measurement Information
    1. 7.1 Timing Diagrams
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Clock Input
      3. 8.3.3 Gain for SFDR, SNR Trade-Off
      4. 8.3.4 Offset Correction
      5. 8.3.5 Digital Output Information
        1. 8.3.5.1 Output Interface
        2. 8.3.5.2 DDR LVDS Outputs
        3. 8.3.5.3 LVDS Output Data and Clock Buffers
        4. 8.3.5.4 Parallel CMOS Interface
        5. 8.3.5.5 CMOS Interface Power Dissipation
        6. 8.3.5.6 Input Overvoltage Indication (OVR Pin)
        7. 8.3.5.7 Output Data Format
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration
      2. 8.4.2 Power-Down
        1. 8.4.2.1 Power-Down Global
        2. 8.4.2.2 Standby
        3. 8.4.2.3 Output Buffer Disable
        4. 8.4.2.4 Input Clock Stop
    5. 8.5 Programming
      1. 8.5.1 Serial Interface
        1. 8.5.1.1 Register Initialization
      2. 8.5.2 Serial Register Readout
    6. 8.6 Register Maps
      1. 8.6.1 Serial Register Map
        1. 8.6.1.1 Summary of High-Performance Modes
        2. 8.6.1.2 Description of Serial Registers
          1. 8.6.1.2.1  Register Address 00h (address = 00h) [reset = 00h]
          2. 8.6.1.2.2  Register Address 01h (address = 01h) [reset = 00h]
          3. 8.6.1.2.3  Register Address 03h (address = 03h) [reset = 00h]
          4. 8.6.1.2.4  Register Address 25h (address = 25h) [reset = 50h]
          5. 8.6.1.2.5  Register Address 26h (address = 26h) [reset = 00h]
          6. 8.6.1.2.6  Register Address 3Dh (address = 3Dh) [reset = 00h]
          7. 8.6.1.2.7  Register Address 3Fh (address = 3Fh) [reset = 00h]
          8. 8.6.1.2.8  Register Address 40h (address = 40h) [reset = 00h]
          9. 8.6.1.2.9  Register Address 41h (address = 41h) [reset = 00h]
          10. 8.6.1.2.10 Register Address 42h (address = 42h) [reset = 08h]
          11. 8.6.1.2.11 Register Address 43h (address = 43h) [reset = 00h]
          12. 8.6.1.2.12 Register Address 4Ah (address = 4Ah) [reset = 00h]
          13. 8.6.1.2.13 Register Address BFh (address = BFh) [reset = 00h]
          14. 8.6.1.2.14 Register Address CFh (address = CFh) [reset = 00h]
          15. 8.6.1.2.15 Register Address DFh (address = DFh) [reset = 00h]
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Drive Circuit Requirements
      2. 9.1.2 Driving Circuit
  10. 10Power Supply Recommendations
    1. 10.1 Power-Supply Sequence
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Design Considerations
        1. 11.1.1.1 Grounding
        2. 11.1.1.2 Supply Decoupling
        3. 11.1.1.3 Exposed Pad
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

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8 Detailed Description

8.1 Overview

The ADS41Bx9 is a family of buffered analog input and ultralow power analog-to-digital converters (ADCs) with maximum sampling rates up to 250 MSPS. The conversion process is initiated by a rising edge of the external input clock and the analog input signal is sampled. The sampled signal is sequentially converted by a series of small resolution stages, with the outputs combined in a digital correction logic block. At every clock edge the sample propagates through the pipeline, resulting in a data latency of 21 clock cycles. The output is available as 14-bit data or 12-bit data, in DDR LVDS mode or CMOS mode, and coded in either straight offset binary or binary twos complement format.

8.2 Functional Block Diagram

ADS41B29 ADS41B49 fbd_41b49_bas486.gif Figure 53. ADS41B49 Block Diagram

8.3 Feature Description

8.3.1 Analog Input

The analog input pins have analog buffers (running off the AVDD_BUF supply) that internally drive the differential sampling circuit. As a result of the analog buffer, the input pins present high input impedance to the external driving source (10-kΩ dc resistance and 3.5-pF input capacitance). The buffer helps to isolate the external driving source from the switching currents of the sampling circuit. This buffering makes driving the buffered inputs easy when compared to an ADC without the buffer.

The input common-mode is set internally using a 5-kΩ resistor from each input pin to 1.7 V, so the input signal can be ac-coupled to the pins. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.375 V) and (VCM – 0.375 V), resulting in a 1.5-VPP differential input swing.

The input sampling circuit has a high 3-dB bandwidth that extends up to 800 MHz (measured from the input pins to the sampled voltage). Figure 54 shows an equivalent circuit for the analog input.

ADS41B29 ADS41B49 ai_ana_in_equiv_cir_bas486.gif
1. CEQ refers to the equivalent input capacitance of the buffer = 4 pF.
2. REQ refers to the REQ buffer = 10 Ω.
3. This equivalent circuit is an approximation and valid for frequencies less than 700 MHz.
Figure 54. Analog Input Equivalent Circuit3

8.3.2 Clock Input

The ADS41Bx9 clock inputs can be driven differentially (sine, LVPECL, or LVDS) or single-ended (LVCMOS), with little or no difference in performance between them. The common-mode voltage of the clock inputs is set to VCM using internal 5-kΩ resistors. This setting allows the use of transformer-coupled drive circuits for sine-wave clock or ac-coupling for LVPECL and LVDS clock sources. Figure 55 shows an equivalent circuit for the input clock.

ADS41B29 ADS41B49 ai_clkin_equiv_cir_bas486.gif
NOTE: CEQ is 1 pF to 3 pF and is the equivalent input capacitance of the clock buffer.
Figure 55. Input Clock Equivalent Circuit

A single-ended CMOS clock can be ac-coupled to the CLKP input, with CLKM connected to ground with a 0.1-μF capacitor, as shown in Figure 56. For best performance, the clock inputs must be driven differentially, reducing susceptibility to common-mode noise. For high input frequency sampling, using a clock source with very low jitter is recommended. Band-pass filtering of the clock source can help reduce the effects of jitter. There is no change in performance with a non-50% duty cycle clock input. Figure 57 shows a differential circuit.

ADS41B29 ADS41B49 ai_drv_cir_1end_bas483.gif Figure 56. Single-Ended Clock Driving Circuit
ADS41B29 ADS41B49 ai_drv_cir_diff_bas483.gif Figure 57. Differential Clock Driving Circuit

8.3.3 Gain for SFDR, SNR Trade-Off

The ADS41Bx9 includes gain settings that can be used to get improved SFDR performance. The gain is programmable from 0 dB to 3.5 dB (in 0.5-dB steps) using the GAIN register bits. For each gain setting, the analog input full-scale range scales proportionally, as shown in Table 1.

The SFDR improvement is achieved at the expense of SNR; for each gain setting, the SNR degrades approximately between 0.5 dB and 1 dB. The SNR degradation is reduced at high input frequencies. As a result, the gain is very useful at high input frequencies because the SFDR improvement is significant with marginal degradation in SNR. Therefore, the gain can be used to trade-off between SFDR and SNR.

After a reset, the gain is enabled with 0dB gain setting. For other gain settings, program the GAIN register bits.

Table 1. Full-Scale Range Across Gains

GAIN (dB) TYPE FULL-SCALE (VPP)
0 Default after reset 1.5
0.5 Programmable gain 1.41
1 Programmable gain 1.33
1.5 Programmable gain 1.26
2 Programmable gain 1.19
2.5 Programmable gain 1.12
3 Programmable gain 1.06
3.5 Programmable gain 1

8.3.4 Offset Correction

The ADS41Bx9 has an internal offset correction algorithm that estimates and corrects dc offset up to ±10 mV. The correction can be enabled using the EN OFFSET CORR serial register bit. When enabled, the algorithm estimates the channel offset and applies the correction every clock cycle. The time constant of the correction loop is a function of the sampling clock frequency. The time constant can be controlled using the OFFSET CORR TIME CONSTANT register bits, as described in Table 2.

Table 2. Time Constant of Offset Correction Loop

OFFSET CORR TIME CONSTANT TIME CONSTANT, TCCLK
(Number of Clock Cycles)
TIME CONSTANT, TCCLK × 1 / fS (sec)(1)
0000 1M 4 ms
0001 2M 8 ms
0010 4M 16.7 ms
0011 8M 33.5 ms
0100 16M 67 ms
0101 32M 134 ms
0110 64M 268 ms
0111 128M 537 ms
1000 256M 1.1 s
1001 512M 2.15 s
1010 1G 4.3 s
1011 2G 8.6 s
1100 Reserved
1101 Reserved
1110 Reserved
1111 Reserved
(1) Sampling frequency, fS = 250 MSPS.

After the offset is estimated, the correction can be frozen by setting FREEZE OFFSET CORR = 1. When frozen, the last estimated value is used for the offset correction of every clock cycle. Note that offset correction is disabled by a default after reset.

After a reset, the offset correction is disabled. To use offset correction set EN OFFSET CORR to 1 and program the required time constant. Figure 58 shows the time response of the offset correction algorithm after it is enabled.

ADS41B29 ADS41B49 ai_tc_offset_converge_bas483.gif Figure 58. Time Response of Offset Correction

8.3.5 Digital Output Information

The ADS41Bx9 provides either 14-bit data or 12-bit data, respectively, and an output clock synchronized with the data.

8.3.5.1 Output Interface

Two output interface options are available: double data rate (DDR) LVDS and parallel CMOS. They can be selected using the LVDS CMOS serial interface register bit or using the DFS pin.

8.3.5.2 DDR LVDS Outputs

In this mode, the data bits and clock are output using low voltage differential signal (LVDS) levels. Two data bits are multiplexed and output on each LVDS differential pair, as illustrated in Figure 59 and Figure 60.

ADS41B29 ADS41B49 ai_ddr_41b29_bas486.gif Figure 59. ADS41B29 LVDS Data Outputs
ADS41B29 ADS41B49 ai_ddr_41b49_bas486.gif Figure 60. ADS41B49 LVDS Data Outputs

Even data bits (D0, D2, D4, and so forth) are output at the falling edge of CLKOUTP and the odd data bits (D1, D3, D5, and so forth) are output at the rising edge of CLKOUTP. Both the rising and falling edges of CLKOUTP must be used to capture all 14 data bits, as shown in Figure 61.

ADS41B29 ADS41B49 ai_tim_ddr_lvds_iface_bas483.gif Figure 61. DDR LVDS Interface

8.3.5.3 LVDS Output Data and Clock Buffers

The equivalent circuit of each LVDS output buffer is shown in Figure 62. After reset, the buffer presents an output impedance of 100Ω to match with the external 100-Ω termination.

The VDIFF voltage is nominally 350 mV, resulting in an output swing of ±350 mV with 100-Ω external termination. The VDIFF voltage is programmable using the LVDS SWING register bits from ±125 mV to ±570 mV.

Additionally, a mode exists to double the strength of the LVDS buffer to support 50-Ω differential termination. This mode can be used when the output LVDS signal is routed to two separate receiver chips, each using a
100-Ω termination. The mode can be enabled using the LVDS DATA STRENGTH and LVDS CLKOUT STRENGTH register bits for data and output clock buffers, respectively.

The buffer output impedance behaves in the same way as a source-side series termination. By absorbing reflections from the receiver end, signal integrity is improved.

ADS41B29 ADS41B49 ai_lvds_buf_equiv_cir_bas483.gif
NOTE: Use the default buffer strength to match 100-Ω external termination (ROUT = 100 Ω). To match with a 50-Ω external termination, set the LVDS STRENGTH bit (ROUT = 50 Ω).
Figure 62. LVDS Buffer Equivalent Circuit

8.3.5.4 Parallel CMOS Interface

In CMOS mode, each data bit is output on a separate pin as the CMOS voltage level, for every clock cycle. The rising edge of the output clock CLKOUT can be used to latch data in the receiver. Figure 63 depicts the CMOS output interface.

Switching noise (caused by CMOS output data transitions) can couple into the analog inputs and degrade SNR. The coupling and SNR degradation increases as the output buffer drive is made stronger. To minimize this degradation, the CMOS output buffers are designed with controlled drive strength. The default drive strength ensures a wide data stable window (even at 250 MSPS) is provided so the data outputs have minimal load capacitance. Using short traces (one to two inches or 2.54 cm to 5.08 cm) terminated with less than 5-pF load capacitance is recommended; see Figure 64.

For sampling frequencies greater than 200 MSPS, using an external clock to capture data is recommended. The delay from input clock to output data and the data valid times are specified for higher sampling frequencies. These timings can be used to delay the input clock appropriately and use it to capture data.

ADS41B29 ADS41B49 ai_cmos_out_iface_bas486.gif Figure 63. CMOS Output Interface
ADS41B29 ADS41B49 ai_cmos_dout_bas486.gif Figure 64. Using the CMOS Data Outputs

8.3.5.5 CMOS Interface Power Dissipation

With CMOS outputs, the DRVDD current scales with the sampling frequency and the load capacitance on every output pin. The maximum DRVDD current occurs when each output bit toggles between 0 and 1 every clock cycle. In actual applications, this condition is unlikely to occur. The actual DRVDD current would be determined by the average number of output bits switching, which is a function of the sampling frequency and the nature of the analog input signal.

Equation 1. Digital Current as a Result of CMOS Output Switching = CL × DRVDD × (N × fAVG)

where

Figure 41 illustrates the current across sampling frequencies at 2-MHz analog input frequency.

8.3.5.6 Input Overvoltage Indication (OVR Pin)

The device has an OVR pin that provides information about analog input overload. At any clock cycle, if the sampled input voltage exceeds the positive or negative full-scale range, the OVR pin goes high. The OVR remains high as long as the overload condition persists. The OVR pin is a CMOS output buffer (running off DRVDD supply), independent of the type of output data interface (DDR LVDS or CMOS).

For a positive overload, the D[13:0] output data bits are 0x3FFF in offset binary output format and 0x1FFF in twos complement output format. For a negative input overload, the output code is 0x0000 in offset binary output format and 0x2000 in twos complement output format.

8.3.5.7 Output Data Format

Two output data formats are supported: twos complement and offset binary. They can be selected using the DATA FORMAT serial interface register bit or controlling the DFS pin in parallel configuration mode. In the event of an input voltage overdrive, the digital outputs go to the appropriate full-scale level.

8.4 Device Functional Modes

8.4.1 Device Configuration

The ADS41Bx9 have several modes that can be configured using a serial programming interface, as described in Table 3, Table 4, and Table 5. In addition, the devices have two dedicated parallel pins for quickly configuring commonly used functions. The parallel pins are DFS (analog 4-level control pin) and OE (digital control pin). The analog control pins can be easily configured using a simple resistor divider (with 10% tolerance resistors).

Table 3. DFS: Analog Control Pin

VOLTAGE APPLIED ON DFS DESCRIPTION
(Data Format, Output Interface)
0, 100 mV / 0 mV Twos complement, DDR LVDS
(3/8) AVDD ± 100 mV Twos complement, parallel CMOS
(5/8) AVDD ± 100 mV Offset binary, parallel CMOS
AVDD, 0 mV / –100 mV Offset binary, DDR LVDS

Table 4. OE: Digital Control Pin

VOLTAGE APPLIED ON OE DESCRIPTION
0 Output data buffers disabled
AVDD Output data buffers enabled

When the serial interface is not used, the SDATA pin can also be used as a digital control pin to place the device in standby mode. To enable this, the RESET pin must be tied high. In this mode, SEN and SCLK do not have any alternative functions. Keep SEN tied high and SCLK tied low on the board.

Table 5. SDATA: Digital Control Pin

VOLTAGE APPLIED ON SDATA DESCRIPTION
0 Normal operation
Logic high Device enters standby

A simple diagram to configure DFS pin is shown in Figure 65.

ADS41B29 ADS41B49 config_par_sen_sclk_bas483.gif Figure 65. Simplified Diagram to Configure the DFS Pin

8.4.2 Power-Down

The ADS41Bx9 has three power-down modes: power-down global, standby, and output buffer disable.

8.4.2.1 Power-Down Global

In this mode, the entire chip (including the ADC, internal reference, and the output buffers) is powered down, resulting in reduced total power dissipation of approximately 7 mW. The output buffers are in a high-impedance state. The wake-up time from the global power-down to data becoming valid in normal mode is typically 100 µs. To enter the global power-down mode, set the PDN GLOBAL register bit.

8.4.2.2 Standby

In this mode, only the ADC is powered down and the internal references are active, resulting in a fast wake-up time of 5 µs. The total power dissipation in standby mode is approximately 200mW. To enter the standby mode, set the STBY register bit.

8.4.2.3 Output Buffer Disable

The output buffers can be disabled and put in a high-impedance state; wake-up time from this mode is fast, approximately 100 ns. This can be controlled using the PDN OBUF register bit or using the OE pin.

8.4.2.4 Input Clock Stop

In addition, the converter enters a low-power mode when the input clock frequency falls below 1 MSPS. The power dissipation is approximately 92 mW.

8.5 Programming

8.5.1 Serial Interface

The analog-to-digital converter (ADC) has a set of internal registers that can be accessed by the serial interface formed by the SEN (serial interface enable), SCLK (serial interface clock), and SDATA (serial interface data) pins. Serially shifting bits into the device is enabled when SEN is low. SDATA serial SDATA are latched at every falling edge of SCLK when SEN is active (low). The serial data are loaded into the register at every 16th SCLK falling edge when SEN is low. In case the word length exceeds a multiple of 16 bits, the excess bits are ignored. Data can be loaded in multiples of 16-bit words within a single active SEN pulse. The first eight bits form the register address and the remaining eight bits are the register data. The interface can work with SCLK frequency from 20 MHz down to very low speeds (a few hertz) and also with non-50% SCLK duty cycle.

8.5.1.1 Register Initialization

After power-up, the internal registers must be initialized to the default values. This initialization can be accomplished in one of two ways:

  1. Either through hardware reset by applying a high pulse on RESET pin (of width greater than 10 ns), as shown in Figure 66; or
  2. By applying a software reset. When using the serial interface, set the RESET bit (D7 in register 0x00) high. This setting initializes the internal registers to the default values and then self-resets the RESET bit low. In this case, the RESET pin is kept low.
ADS41B29 ADS41B49 tim_serial_iface_bas483.gif Figure 66. Serial Interface Timing

Table 6. Serial Interface Timing Characteristics(2)(1)

MIN TYP MAX UNIT
fSCLK SCLK frequency (equal to 1 / tSCLK) > dc 20 MHz
tSLOADS SEN to SCLK setup time 25 ns
tSLOADH SCLK to SEN hold time 25 ns
tDSU SDATA setup time 25 ns
tDH SDATA hold time 25 ns
(1) Typical values are at 25°C, minimum and maximum values for the ADS41B49 are specified across the ambient temperature range of
TA, MIN = –40°C to TA, MAX = 105°C, AVDD = 1.8 V, and DRVDD = 1.8 V.
(2) Typical values are at 25°C, minimum and maximum values for the ADS41B29 are specified across the ambient temperature range of
TA, MIN = –40°C to TA, MAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.8 V.

8.5.2 Serial Register Readout

The serial register readout function allows the contents of the internal registers to be read back on the OVR_SDOUT pin. This readback may be useful as a diagnostic check to verify the serial interface communication between the external controller and the ADC.

After power-up and device reset, the OVR_SDOUT pin functions as an over-range indicator pin by default. When the readout mode is enabled, OVR_SDOUT outputs the contents of the selected register serially:

  1. Set the READOUT register bit to 1. This setting puts the device in serial readout mode and disables any further writes to the internal registers except the register at address 0. Note that the READOUT bit itself is also located in register 0. The device can exit readout mode by writing READOUT = 0. Only the contents of the register at address 0 cannot be read in the register readout mode.
  2. Initiate a serial interface cycle specifying the address of the register (A7 to A0) whose content has to be read.
  3. The device serially outputs the contents (D7 to D0) of the selected register on the OVR_SDOUT pin.
  4. The external controller can latch the contents at the falling edge of SCLK.
  5. To exit the serial readout mode, the reset register bit READOUT = 0 enables writes into all registers of the device. At this point, the OVR_SDOUT pin becomes an over-range indicator pin.

Figure 67 shows the process of reading out register contents on the OVR_SDOUT pin, using register 43h as example.

ADS41B29 ADS41B49 tim_serial_readout_bas483.gif
1. The OVR_SDOUT pin functions as OVR (READOUT = 0).
2. The OVR_SDOUT pin functions as a serial readout (READOUT = 1).
Figure 67. Serial Readout Timing Diagram

8.6 Register Maps

8.6.1 Serial Register Map

Table 7 summarizes the functions supported by the serial interface.

Table 7. Serial Interface Register Map(1)

REGISTER ADDRESS DEFAULT VALUE AFTER RESET REGISTER DATA
A[7:0] (Hex) D[7:0] (Hex) D7 D6 D5 D4 D3 D2 D1 D0
00 00 0 0 0 0 0 0 RESET READOUT
01 00 LVDS SWING 0 0
03 00 0 0 0 0 0 0 HIGH PERF MODE 1
25 50 GAIN 0 TEST PATTERNS
26 00 0 0 0 0 0 0 LVDS CLKOUT STRENGTH LVDS DATA STRENGTH
3D 00 DATA FORMAT EN OFFSET CORR 0 0 0 0 0
3F 00 0 0 CUSTOM PATTERN D[13:8]
40 00 CUSTOM PATTERN D[7:0]
41 00 LVDS CMOS CMOS CLKOUT STRENGTH EN CLKOUT RISE CLKOUT RISE POSN EN CLKOUT FALL
42 08 CLKOUT FALL POSN 0 0 1 STBY 0 0
43 00 0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING
4A 00 0 0 0 0 0 0 0 HIGH PERF MODE 2
BF 00 OFFSET PEDESTAL 0 0
CF 00 FREEZE OFFSET CORR 0 OFFSET CORR TIME CONSTANT 0 0
DF 00 0 0 LOW SPEED 0 0 0 0
(1) Multiple functions in a register can be programmed in a single write operation.

8.6.1.1 Summary of High-Performance Modes

Table 8 lists the location and functions of high-performance mode registers in the device.

Table 8. High-Performance Modes Summary(4)(5)(6)

MODE LOCATION FUNCTION
MODE 1 Register address = 03h, register data = 03h Set the MODE 1 register bits to get the best performance across sample clock and input signal frequencies.
MODE 2 Register address = 4Ah, register data = 01h Set the MODE 2 register bit to get the best performance at high input signal frequencies greater than 230 MHz.

8.6.1.2 Description of Serial Registers

For best performance, two special mode register bits must be enabled:

HI PERF MODE 1 and HI PERF MODE 2.

8.6.1.2.1 Register Address 00h (address = 00h) [reset = 00h]

Figure 68. Register Address 00h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 RESET READOUT
Bits 7-2 Always write 0
Bit 1 RESET: Software reset applied
This bit resets all internal registers to the default values and self-clears to 0 (default = 1).
Bit 0 READOUT: Serial readout
This bit sets the serial readout of the registers.
0 = Serial readout of registers disabled; the OVR_SDOUT pin functions as an over-voltage indicator.
1 = Serial readout enabled; the OVR_SDOUT pin functions as a serial data readout.

8.6.1.2.2 Register Address 01h (address = 01h) [reset = 00h]

Figure 69. Register Address 01h
7 6 5 4 3 2 1 0
LVDS SWING 0 0
Bits 7-2 LVDS SWING: LVDS swing programmability(1)
000000 = Default LVDS swing; ±350 mV with external 100-Ω termination
011011 = LVDS swing increases to ±410 mV
110010 = LVDS swing increases to ±465 mV
010100 = LVDS swing increases to ±570 mV
111110 = LVDS swing decreases to ±200 mV
001111 = LVDS swing decreases to ±125 mV
Bits 1-0 Always write 0
(1) The EN LVDS SWING register bits must be set to enable LVDS swing control.

8.6.1.2.3 Register Address 03h (address = 03h) [reset = 00h]

Figure 70. Register Address 03h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 HI PERF MODE 1
Bits 7-2 Always write 0
Bits 1-0 HI PERF MODE 1: High performance mode 1
00 = Default performance after reset
01 = Do not use
10 = Do not use
11 = For best performance across sampling clock and input signal frequencies, set the HIGH PERF MODE 1 bits

8.6.1.2.4 Register Address 25h (address = 25h) [reset = 50h]

Figure 71. Register Address 25h
7 6 5 4 3 2 1 0
GAIN 0 TEST PATTERNS
Bits 7-4 GAIN: Gain programmability
These bits set the gain programmability in 0.5-dB steps.
0000, 0001, 0010, 0011, 0100 = Do not use
0101 = 0-dB gain (default after reset)
0110 = 0.5-dB gain
0111 = 1-dB gain
1000 = 1.5-dB gain
1001 = 2-dB gain
1010 = 2.5-dB gain
1011 = 3-dB gain
1100 = 3.5-dB gain
Bit 3 Always write 0
Bits 2-0 TEST PATTERNS: Data capture
These bits verify data capture.
000 = Normal operation
001 = Outputs all 0s
010 = Outputs all 1s
011 = Outputs toggle pattern
In the ADS41B49, output data D[13:0] is an alternating sequence of 01010101010101 and 10101010101010.
In the ADS41B29, output data D[11:0] is an alternating sequence of 010101010101 and 101010101010.
100 = Outputs digital ramp
In ADS41B46, output data increments by one LSB (14-bit) every clock cycle from code 0 to
code 16383
In ADS41B26, output data increments by one LSB (12-bit) every 4th clock cycle from code 0 to code 4095
101 = Output custom pattern (use registers 0x3F and 0x40 for setting the custom pattern)
110 = Unused
111 = Unused

8.6.1.2.5 Register Address 26h (address = 26h) [reset = 00h]

Figure 72. Register Address 26h
7 6 5 4 3 2 1 0
0 0 0 0 0 0 LVDS CLKOUT STRENGTH LVDS DATA STRENGTH
Bits 7-2 Always write 0
Bit 1 LVDS CLKOUT STRENGTH: LVDS output clock buffer strength
This bit determines the external termination to be used with the LVDS output clock buffer.
0 = 100-Ω external termination (default strength)
1 = 50-Ω external termination (2x strength)
Bit 0 LVDS DATA STRENGTH: LVDS data buffer strength
This bit determines the external termination to be used with all of the LVDS data buffers.
0 = 100-Ω external termination (default strength)
1 = 50-Ω external termination (2x strength)

8.6.1.2.6 Register Address 3Dh (address = 3Dh) [reset = 00h]

Figure 73. Register Address 3Dh
7 6 5 4 3 2 1 0
DATA FORMAT EN OFFSET CORR 0 0 0 0 0
Bits 7-6 DATA FORMAT: Data format selection
These bits selects the data format.
00 = The DFS pin controls data format selection
10 = Twos complement
11 = Offset binary
Bit 5 ENABLE OFFSET CORR: Offset correction setting
This bit sets the offset correction.
0 = Offset correction disabled
1 = Offset correction enabled
Bits 4-0 Always write 0

8.6.1.2.7 Register Address 3Fh (address = 3Fh) [reset = 00h]

Figure 74. Register Address 3Fh
7 6 5 4 3 2 1 0
0 0 CUSTOM PATTERN D13 CUSTOM PATTERN D12 CUSTOM PATTERN D11 CUSTOM PATTERN D10 CUSTOM PATTERN D9 CUSTOM PATTERN D8
Bits 7-6 Always write 0
Bits 5-0 CUSTOM PATTERN(1)
These bits set the custom pattern.

8.6.1.2.8 Register Address 40h (address = 40h) [reset = 00h]

Figure 75. Register Address 40h
7 6 5 4 3 2 1 0
CUSTOM PATTERN D7 CUSTOM PATTERN D6 CUSTOM PATTERN D5 CUSTOM PATTERN D4 CUSTOM PATTERN D3 CUSTOM PATTERN D2 CUSTOM PATTERN D1 CUSTOM PATTERN D0
Bits 7-0 CUSTOM PATTERN(1)
These bits set the custom pattern.
(1) For the ADS41B4x, output data bits 13 to 0 are CUSTOM PATTERN D[13:0]. For the ADS41B2x, output data bits 11 to 0 are CUSTOM PATTERN D[13:2].

8.6.1.2.9 Register Address 41h (address = 41h) [reset = 00h]

Figure 76. Register Address 41h
7 6 5 4 3 2 1 0
LVDS CMOS CMOS CLKOUT STRENGTH EN CLKOUT RISE CLKOUT RISE POSN EN CLKOUT FALL
Bits 7-6 LVDS CMOS: Interface selection
These bits select the interface.
00, 10 = The DFS pin controls the selection of either LVDS or CMOS interface
01 = DDR LVDS interface
11 = Parallel CMOS interface
Bits 5-4 CMOS CLKOUT STRENGTH
Controls strength of CMOS output clock only.
00 = Maximum strength (recommended and used for specified timings)
01 = Medium strength
10 = Low strength
11 = Very low strength
Bit 3 ENABLE CLKOUT RISE
0 = Disables control of output clock rising edge
1 = Enables control of output clock rising edge
Bits 2-1 CLKOUT RISE POSN: CLKOUT rise control
Controls position of output clock rising edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 500 ps, hold increases by 500 ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200 ps, hold increases by 200 ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 100 ps, hold increases by 100 ps
10 = Setup reduces by 200 ps, hold increases by 200 ps
11 = Setup reduces by 1.5 ns, hold increases by 1.5 ns
Bit 0 ENABLE CLKOUT FALL
0 = Disables control of output clock fall edge
1 = Enables control of output clock fall edge

8.6.1.2.10 Register Address 42h (address = 42h) [reset = 08h]

Figure 77. Register Address 42h
7 6 5 4 3 2 1 0
CLKOUT FALL POSN 0 0 1 STBY 0 0
Bits 7-6 CLKOUT FALL POSN
Controls position of output clock falling edge
LVDS interface:
00 = Default position (timings are specified in this condition)
01 = Setup reduces by 400 ps, hold increases by 400 ps
10 = Data transition is aligned with rising edge
11 = Setup reduces by 200 ps, hold increases by 200 ps
CMOS interface:
00 = Default position (timings are specified in this condition)
01 = Falling edge is advanced by 100 ps
10 = Falling edge is advanced by 200 ps
11 = Falling edge is advanced by 1.5 ns
Bits 5-4 Always write 0
Bit 3 Always write 1
Bit 2 STBY: Standby mode
This bit sets the standby mode.
0 = Normal operation
1 = Only the ADC and output buffers are powered down; internal reference is active; wake-up time from standby is fast
Bits 1-0 Always write 0

8.6.1.2.11 Register Address 43h (address = 43h) [reset = 00h]

Figure 78. Register Address 43h
7 6 5 4 3 2 1 0
0 PDN GLOBAL 0 PDN OBUF 0 0 EN LVDS SWING
Bit 7 Always write 0
Bit 6 PDN GLOBAL: Power-down
This bit sets the state of operation.
0 = Normal operation
1 = Total power down; the ADC, internal references, and output buffers are powered down; slow wake-up time.
Bit 5 Always write 0
Bit 4 PDN OBUF: Power-down output buffer
This bit set the output data and clock pins.
0 = Output data and clock pins enabled
1 = Output data and clock pins powered down and put in high- impedance state
Bits 3-2 Always write 0
Bits 1-0 EN LVDS SWING: LVDS swing control
00 = LVDS swing control using LVDS SWING register bits is disabled
01, 10 = Do not use
11 = LVDS swing control using LVDS SWING register bits is enabled

8.6.1.2.12 Register Address 4Ah (address = 4Ah) [reset = 00h]

Figure 79. Register Address 4Ah
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 HI PERF MODE 2
Bits 7-1 Always write 0
Bit 0 HI PERF MODE 2: High performance mode 2
This bit is recommended for high input signal frequencies greater than 230 MHz.
0 = Default performance after reset
1 = For best performance with high-frequency input signals, set the HIGH PERF MODE 2 bit

8.6.1.2.13 Register Address BFh (address = BFh) [reset = 00h]

Figure 80. Register Address BFh
7 6 5 4 3 2 1 0
OFFSET PEDESTAL 0 0
Bits 7-2 OFFSET PEDESTAL
These bits set the offset pedestal. For the ADS41B49, bits 7-2 set the pedestal; for the ADS41B29, bits 7-4 set the pedestal.
When the offset correction is enabled, the final converged value after the offset is corrected is the ADC mid-code value. A pedestal can be added to the final converged value by programming these bits.
ADS41Bx9 VALUE PEDESTAL
011111
011110
011101

000000

111111
111110

100000
31 LSB
30 LSB
29 LSB

0 LSB

–1 LSB
–2 LSB

–32 LSB
Bits 1-0 Always write 0

8.6.1.2.14 Register Address CFh (address = CFh) [reset = 00h]

Figure 81. Register Address CFh
7 6 5 4 3 2 1 0
FREEZE OFFSET CORR 0 OFFSET CORR TIME CONSTANT 0 0
Bit 7 FREEZE OFFSET CORR
This bit sets the freeze offset correction.
0 = Estimation of offset correction is not frozen (bit EN OFFSET CORR must be set)
1 = Estimation of offset correction is frozen (bit EN OFFSET CORR must be set). When frozen, the last estimated value is used for offset correction every clock cycle; see the Offset Correction section.
Bit 6 Always write 0
Bits 5-2 OFFSET CORR TIME CONSTANT
These bits set the offset correction time constant for the correction loop time constant in number of clock cycles.
VALUE TIME CONSTANT (Number of Clock Cycles)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1M
2M
4M
8M
16M
32M
64M
128M
256M
512M
1G
2G
Bits 1-0 Always write 0

8.6.1.2.15 Register Address DFh (address = DFh) [reset = 00h]

Figure 82. Register Address DFh
7 6 5 4 3 2 1 0
0 0 LOW SPEED 0 0 0 0
Bits 7-6 Always write 0
Bits 5-4 LOW SPEED: Low-speed mode
00, 01, 10 = Low-speed mode disabled (default state after reset); this setting is recommended for sampling rates greater than 80 MSPS.
11 = Low-speed mode enabled; this setting is recommended for sampling rates less than or equal to 80 MSPS.
Bits 3-0 Always write 0