JAJSCL4 November   2016 ADS7049-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Digital Voltage Levels
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Analog Input
      3. 8.3.3 ADC Transfer Function
      4. 8.3.4 Serial Interface
    4. 8.4 Device Functional Modes
      1. 8.4.1 Offset Calibration
        1. 8.4.1.1 Offset Calibration on Power-Up
        2. 8.4.1.2 Offset Calibration During Normal Operation
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Low Distortion Charge Kickback Filter Design
        2. 9.2.2.2 Input Amplifier Selection
        3. 9.2.2.3 Reference Circuit
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
    1. 10.1 AVDD and DVDD Supply Recommendations
    2. 10.2 Estimating Digital Power Consumption
    3. 10.3 Optimizing Power Consumed by the Device
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 コミュニティ・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Specifications

6.1 Absolute Maximum Ratings(1)

MIN MAX UNIT
AVDD to GND –0.3 3.9 V
DVDD to GND –0.3 3.9 V
AINP to GND –0.3 AVDD + 0.3 V
AINM to GND –0.3 0.3 V
Digital input voltage to GND –0.3 DVDD + 0.3 V
Storage temperature, Tstg –60 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 ±1000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
AVDD Analog supply voltage range 2.35 3.6 V
DVDD Digital supply voltage range 1.65 3.6 V
TA Operating free-air temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) ADS7049-Q1 UNIT
DCU (VSSOP)
8 PINS
RθJA Junction-to-ambient thermal resistance 181.8 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.8 °C/W
RθJB Junction-to-board thermal resistance 73.9 °C/W
ψJT Junction-to-top characterization parameter 1.0 °C/W
ψJB Junction-to-board characterization parameter 73.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

at TA = –40°C to 125°C, AVDD = 3 V, DVDD = 1.65 V to 3.6 V, fSAMPLE = 2 MSPS, and VAINM = 0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input voltage span(1) 0 AVDD V
Absolute input voltage range AINP to GND –0.1 AVDD + 0.1 V
AINM to GND –0.1 0.1
CS Sampling capacitance 15 pF
SYSTEM PERFORMANCE
Resolution 12 Bits
NMC No missing codes 12 Bits
INL Integral nonlinearity AVDD = 3 V –1 ±0.5 1 LSB(2)
DNL Differential nonlinearity AVDD = 3 V –0.99 ±0.5 1 LSB
EO Offset error Uncalibrated ±12 LSB
Calibrated(6) AVDD = 3 V –3 ±0.5 3
dVOS/dT Offset error drift with temperature ±5 ppm/°C
EG Gain error AVDD = 3 V –0.1 ±0.05 0.1 %FS
Gain error drift with temperature No calibration ±2 ppm/°C
SAMPLING DYNAMICS
tACQ Acquisition time 90 ns
Maximum throughput rate 32-MHz SCLK, AVDD = 2.35 V to 3.6 V 2 MHz
DYNAMIC CHARACTERISTICS
SNR Signal-to-noise ratio(4) fIN = 2 kHz, AVDD = 3 V 68 70 dB
THD Total harmonic distortion(4)(3) fIN = 2 kHz, AVDD = 3 V –80 dB
SINAD Signal-to-noise and distortion(4) fIN = 2 kHz, AVDD = 3 V 67.5 69.5 dB
SFDR Spurious-free dynamic range(4) fIN = 2 kHz, AVDD = 3 V 80 dB
BW(fp) Full-power bandwidth At –3 dB, AVDD = 3 V 25 MHz
DIGITAL INPUT/OUTPUT (CMOS Logic Family)
VIH High-level input voltage(5) 0.65 × DVDD DVDD + 0.3 V
VIL Low-level input voltage(5) –0.3 0.35 × DVDD V
VOH High-level output voltage(5) At Isource = 500 µA 0.8 × DVDD DVDD V
At Isource = 2 mA DVDD – 0.45 DVDD
VOL Low-level output voltage(5) At Isink = 500 µA 0 0.2 × DVDD V
At Isink = 2 mA 0 0.45
POWER-SUPPLY REQUIREMENTS
AVDD Analog supply voltage 2.35 3 3.6 V
DVDD Digital I/O supply voltage 1.65 3 3.6 V
IAVDD Analog supply current At 2 MSPS with AVDD = 3 V 380 460 µA
IDVDD Digital supply current AVDD = 3 V, no load, no transitions 10 µA
PD Power dissipation At 2 MSPS with AVDD = 3 V 1.14 1.38 mW
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Calculated on the first nine harmonics of the input frequency.
(4) All specifications expressed in decibels (dB) refer to the full-scale input (FSR) and are tested with an input signal 0.5 dB below full-scale, unless otherwise specified.
(5) Digital voltage levels comply with the JESD8-7A standard for DVDD from 1.65 V to 1.95 V; see the Digital Voltage Levels section for more details.
(6) See the Offset Calibration section for more details.

6.6 Timing Requirements

all specifications are at TA = –40°C to 125°C, AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF (unless otherwise specified)
MIN TYP MAX UNIT
tACQ Acquisition time 90 ns
fSCLK SCLK frequency 0.016 32 MHz
tSCLK SCLK period 31.25 ns
tPH_CK SCLK high time 0.45 0.55 tSCLK
tPL_CK SCLK low time 0.45 0.55 tSCLK
tPH_CS CS high time 30 ns
tSU_CSCK Setup time: CS falling to SCLK falling 12 ns
tD_CKCS Delay time: last SCLK falling to CS rising 10 ns

6.7 Switching Characteristics

all specifications are at TA = –40°C to 125°C, AVDD = 2.35 V to 3.6 V, DVDD = 1.65 V to 3.6 V, and CLOAD on SDO = 20 pF (unless otherwise specified)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fTHROUGHPUT Throughput 2 MSPS
tCYCLE Cycle time 0.5 µs
tCONV Conversion time 12.5 × tSCLK + tSU_CSCK ns
tDV_CSDO Delay time: CS falling to data enable 10 ns
tD_CKDO Delay time: SCLK falling to (next) data valid on DOUT AVDD = 2.35 V to 3.6 V 25 ns
tDZ_CSDO Delay time: CS rising to DOUT going to tri-state 5 ns
ADS7049-Q1 tim_spi_bas608_B.gif Figure 1. Timing Diagram

6.8 Typical Characteristics

at TA = 25°C, AVDD = 3 V, DVDD = 1.8 V, and fSAMPLE = 2 MSPS (unless otherwise noted)
ADS7049-Q1 D001_SBAS763.gif
SNR = 70.29 dB, THD = –84.04 dB, fIN = 2 kHz,
number of samples = 65536
Figure 2. Typical FFT
ADS7049-Q1 D003_SBAS763.gif
fIN = 2 kHz
Figure 4. SNR and SINAD vs Temperature
ADS7049-Q1 D005_SBAS763.gif
fIN = 2 kHz
Figure 6. SNR and SINAD vs Reference Voltage (AVDD)
ADS7049-Q1 D007_SBAS763.gif
fIN = 2 kHz
Figure 8. SFDR vs Temperature
ADS7049-Q1 D009_SBAS763.gif
Figure 10. SFDR vs Input Frequency
ADS7049-Q1 D011_SBAS763.gif
fIN = 2 kHz
Figure 12. SFDR vs Reference Voltage (AVDD)
ADS7049-Q1 D013_SBAS763.gif
Figure 14. Offset vs Temperature
ADS7049-Q1 D015_SBAS763.gif
Figure 16. Gain Error vs Temperature
ADS7049-Q1 D017_SBAS763.gif
AVDD = 3 V
Figure 18. Typical DNL
ADS7049-Q1 D021_SBAS763.gif
Figure 20. DNL vs Temperature
ADS7049-Q1 D023_SBAS763.gif
Figure 22. INL vs Temperature
ADS7049-Q1 D025_SBAS763.gif
fSample = 2 MSPS
Figure 24. AVDD Supply Current vs Temperature
ADS7049-Q1 D027_SBAS763.gif
fSample = 2 MSPS
Figure 26. AVDD Supply Current vs Supply Voltage
ADS7049-Q1 D029_SBAS763.gif
fIN = 2 kHz
Figure 28. ENOB vs Sampling Rate
ADS7049-Q1 D031_SBAS763.gif
fIN = 2 kHz
Figure 30. SINAD vs Sampling Rate
ADS7049-Q1 D002_SBAS763.gif
SNR = 69.92 dB, THD = –80.05 dB, fIN = 250 kHz,
number of samples = 65536
Figure 3. Typical FFT
ADS7049-Q1 D004_SBAS763.gif
Figure 5. SNR and SINAD vs Input Frequency
ADS7049-Q1 D006_SBAS763.gif
fIN = 2 kHz
Figure 7. THD vs Temperature
ADS7049-Q1 D008_SBAS763.gif
Figure 9. THD vs Input Frequency
ADS7049-Q1 D010_SBAS763.gif
fIN = 2 kHz
Figure 11. THD vs Reference Voltage (AVDD)
ADS7049-Q1 D012_SBAS763.gif
Mean code = 2046.92, sigma = 0.42
Figure 13. DC Input Histogram
ADS7049-Q1 D014_SBAS763.gif
Figure 15. Offset vs Reference Voltage (AVDD)
ADS7049-Q1 D016_SBAS763.gif
Figure 17. Gain Error vs Reference Voltage (AVDD)
ADS7049-Q1 D018_SBAS763.gif
AVDD = 3 V
Figure 19. Typical INL
ADS7049-Q1 D022_SBAS763.gif
Figure 21. DNL vs Reference Voltage (AVDD)
ADS7049-Q1 D024_SBAS763.gif
Figure 23. INL vs Reference Voltage (AVDD)
ADS7049-Q1 D026_SBAS763.gif
Figure 25. AVDD Supply Current vs Throughput
ADS7049-Q1 D028_SBAS763.gif
Figure 27. AVDD Static Current vs Temperature
ADS7049-Q1 D030_SBAS763.gif
fIN = 2 kHz
Figure 29. SNR vs Sampling Rate
ADS7049-Q1 D032_SBAS763.gif
fIN = 2 kHz
Figure 31. THD vs Sampling Rate