SLAS468A June   2005  – August 2016 ADS7887 , ADS7888

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Companion Products
  6. Device Comparison
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics - ADS7887
    6. 8.6 Electrical Characteristics - ADS7888
    7. 8.7 Timing Requirements
    8. 8.8 Typical Characteristics
      1. 8.8.1 ADS7887 and ADS7888
      2. 8.8.2 ADS7887 Only
      3. 8.8.3 ADS7888 Only
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Driving the VIN and VDD Pins of the ADS7887 and ADS7888
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 ADS7887 Operation
      2. 9.3.2 ADS7888 Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Down Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Related Links
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

9 Detailed Description

9.1 Overview

The ADS788x devices are ADC converters. The serial interface in each device is controlled by the CS and SCLK signals for easy interface with microprocessors and DSPs. The input signal is sampled with the falling edge of CS, and SCLK is used for conversion and serial data output. They both operate in a wide supply range from 2.35 V to 5.25 V and low power consumption makes them suitable for battery-powered applications.

9.1.1 Driving the VIN and VDD Pins of the ADS7887 and ADS7888

The VIN input to the ADS7887 and ADS7888 must be driven with a low impedance source. In most cases additional buffers are not required. In cases where the source impedance exceeds 200 Ω, using a buffer would help achieve the rated performance of the converter. The THS4031 is a good choice for the driver amplifier buffer.

The reference voltage for the ADS7887 and ADS7888 A/D converters are derived from the supply voltage internally. The devices offer limited low-pass filtering functionality on-chip. The supply to these converters must be driven with a low impedance source and must be decoupled to the ground. A 1-µF storage capacitor and a 10-nF decoupling capacitor must be placed close to the device. Wide, low impedance traces must be used to connect the capacitor to the pins of the device. The ADS7887 and ADS7888 draw very little current from the supply lines. The supply line can be driven by either:

  • Directly from the system supply.
  • A reference output from a low drift and low dropout reference voltage generator like REF3030 or REF3130. The ADS7887 and ADS7888 can operate off a wide range of supply voltages. The actual choice of the reference voltage generator would depend upon the system. Figure 41 shows one possible application circuit.
  • A low-pass filtered version of the system supply followed by a buffer like the zero-drift OPA735 can also be used in cases where the system power supply is noisy. Take care to ensure that the voltage at the VDD input does not exceed 7 V (especially during power up) to avoid damage to the converter. This can be done easily using single-supply CMOS amplifiers like the OPA735. Figure 42 shows one possible application circuit.
ADS7887 ADS7888 in_sch_las468.gif Figure 31. Typical Equivalent Sampling Circuit

9.2 Functional Block Diagram

ADS7887 ADS7888 bd_las468.gif

9.3 Feature Description

9.3.1 ADS7887 Operation

The cycle begins with the falling edge of CS. This point is indicated as a in Figure 32. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 4 leading zeros, followed by 10-bit data in MSB first format and padded by 2 lagging zeros.

The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded with two lagging zeros as shown in Figure 32. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 14th falling edge of SCLK. The device enters the acquisition phase on the first rising edge of SCLK after the 13th falling edge. This point is indicated by b in Figure 32.

CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle (refer to Power-Down Mode for more details). CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.

The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on power-up sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in Specifications.

ADS7887 ADS7888 tim_87_las468.gif Figure 32. ADS7887 Interface Timing Diagram

9.3.2 ADS7888 Operation

The cycle begins with the falling edge of CS . This point is indicated as a in Figure 33. With the falling edge of CS, the input signal is sampled and the conversion process is initiated. The device outputs data while the conversion is in progress. The data word contains 4 leading zeros, followed by 8-bit data in MSB first format and padded by 4 lagging zeros.

The falling edge of CS clocks out the first zero, and a zero is clocked out on every falling edge of the clock until the third edge. Data is in MSB first format with the MSB being clocked out on the 4th falling edge. Data is padded with four lagging zeros as shown in Figure 33. On the 16th falling edge of SCLK, SDO goes to the 3-state condition. The conversion ends on the 12th falling edge of SCLK. The device enters the acquisition phase on the first rising edge of SCLK after the 11th falling edge. This point is indicated by b in Figure 33.

CS can be asserted (pulled high) after 16 clocks have elapsed. It is necessary not to start the next conversion by pulling CS low until the end of the quiet time (tq) after SDO goes to 3-state. To continue normal operation, it is necessary that CS is not pulled high until point b. Without this, the device does not enter the acquisition phase and no valid data is available in the next cycle (refer to Power-Down Mode for more details). CS going high any time after the conversion start aborts the ongoing conversion and SDO goes to 3-state.

The high level of the digital input to the device is not limited to device VDD. This means the digital input can go as high as 5.25 V when the device supply is 2.35 V. This feature is useful when digital signals are coming from another circuit with different supply levels. Also, this relaxes the restriction on power-up sequencing. However, the digital output levels (VOH and VOL) are governed by VDD as listed in Specifications.

ADS7887 ADS7888 tim_88_las468.gif Figure 33. ADS7888 Interface Timing Diagram

As shown in Figure 34, the ADS7888 can achieve 1.5-MSPS throughput. CS can be pulled high after the 12th falling edge (with a 25-MHz SCLK). SDO goes to 3-state after the LSB (as CS is high). CS can be pulled low at the end of the quiet time (tq) after SDO goes to 3-state.

ADS7887 ADS7888 tim_12_las468.gif Figure 34. ADS7888 Interface Timing Diagram, Data Transfer With 12-Clock Frame

9.4 Device Functional Modes

9.4.1 Power-Down Mode

The device enters power-down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th SCLK falling edge. Ongoing conversion stops and SDO goes to 3-state under this power-down condition as shown in Figure 35.

ADS7887 ADS7888 ent_pdm_las468.gif Figure 35. Entering Power-Down Mode

A dummy cycle with CS low for more than 10 SCLK falling edges brings the device out of power-down mode. For the device to come to the fully powered-up condition it takes 0.8 µs. CS can be pulled high any time after the 10th falling edge as shown in Figure 36. It is not necessary to continue until the 16th clock if the next conversion starts 0.8 µs after CS going low of the dummy cycle and the quiet time (tq) condition is met.

ADS7887 ADS7888 ex_pdm_las468.gif Figure 36. Exiting Power-Down Mode