JAJSPF5 April   2024 ADS9813

ADVANCE INFORMATION  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Inputs
        1. 6.3.1.1 Input Clamp Protection Circuit
        2. 6.3.1.2 Programmable Gain Amplifier (PGA)
        3. 6.3.1.3 Wide-Common-Mode Voltage Rejection Circuit
      2. 6.3.2 ADC Transfer Function
      3. 6.3.3 ADC Sampling Clock Input
      4. 6.3.4 Synchronizing Multiple ADCs
      5. 6.3.5 Reference Voltage
      6. 6.3.6 Test Patterns for Data Interface
        1. 6.3.6.1 Fixed Pattern
        2. 6.3.6.2 Digital Ramp
        3. 6.3.6.3 Alternating Test Pattern
    4. 6.4 Device Functional Modes
      1. 6.4.1 Reset
      2. 6.4.2 Power-Down
      3. 6.4.3 Initialization Sequence
      4. 6.4.4 Normal Operation
    5. 6.5 Programming
      1. 6.5.1 Register Write
      2. 6.5.2 Register Read
      3. 6.5.3 Multiple Devices in a Daisy-Chain Topology for SPI Configuration
        1. 6.5.3.1 Register Write With Daisy-Chain
        2. 6.5.3.2 Register Read With Daisy-Chain
  8. 7 Register Map
    1. 7.1 Register Bank 0
    2. 7.2 Register Bank 1
    3. 7.3 Register Bank 2
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Parametric Measurement Unit (PMU)
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-20210423-CA0I-T5WB-GNFW-DCC090LWSDWQ-low.svg Figure 4-1 RSH Package, 56-Pin VQFN (Top View)
Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME NO.
AIN1M 55 AI Analog input channel 1, negative input.
AIN1P 54 AI Analog input channel 1, positive input.
AIN2M 2 AI Analog input channel 2, negative input.
AIN2P 1 AI Analog input channel 2, positive input.
AIN3M 4 AI Analog input channel 3, negative input.
AIN3P 3 AI Analog input channel 3, positive input.
AIN4M 6 AI Analog input channel 4, negative input.
AIN4P 5 AI Analog input channel 4, positive input.
AIN5M 10 AI Analog input channel 5, negative input.
AIN5P 9 AI Analog input channel 5, positive input.
AIN6M 12 AI Analog input channel 6, negative input.
AIN6P 11 AI Analog input channel 6, positive input.
AIN7M 14 AI Analog input channel 7, negative input.
AIN7P 13 AI Analog input channel 7, positive input.
AIN8M 17 AI Analog input channel 8, negative input.
AIN8P 16 AI Analog input channel 8, positive input.
AVDD_5V 15, 56 P 5V analog supply. Connect 1µF and 0.1µF decoupling capacitors to GND.
CS 25 DI Chip-select input for the SPI interface configuration; active low. This pin has an internal 100kΩ pullup resistor to IOVDD.
D0 34 DO Serial output data lane 0.
D1 35 DO Serial data output lane 1.
D2 36 DO Serial data output lane 2.
D3 37 DO Serial data output lane 3.
DCLKOUT 33 DO Clock output for the data interface.
FCLKOUT 40 DO Frame synchronization output for the data interface.
GND 7, 23, 46 P Ground.
IOGND 29, 42 P Ground for the digital interface. Connect to ground externally.
IOVDD 30, 41 P Digital I/O supply for the data interface. Connect 1µF and 0.1µF decoupling capacitors to GND.
NC 20, 38, 39, 50, 51 — Not connected. No external connection.
PWDN 32 DI Power-down control; active low. PWDN has an internal 100kΩ pullup resistor to the digital interface supply.
REFIO 52 AI/AO REFIO acts as an internal reference output when the internal reference is enabled. REFIO functions as an input pin for the external reference when the internal reference is disabled. Connect a 10µF decoupling capacitor to the REFM pins.
REFM 8, 18, 53 AI Reference ground potential. Connect to GND.
REFOUT_2V5 19 AO 2.5V reference output. Connect a decoupling 10µF capacitor to the REFM pins.
RESET 31 DI Reset input for the device; active low. RESET has an internal 100kΩ pullup resistor to the digital interface supply.
SCLK 26 DI Serial clock input for the configuration interface. SCLK has an internal 100kΩ pulldown resistor to the digital interface ground.
SDI/EXTREF 27 DI SDI is a multifunction logic input. Pin function is determined by the SPI_EN pin. SDI has an internal 100kΩ pulldown resistor to GND.
SPI_EN = 0b: SDI is the logic input to select between the internal or external reference. Connect SDI to GND for the external reference. Connect SDI to IOVDD for the internal reference.
SPI_EN = 1b: Serial data input for the configuration interface.
SDO 28 DO Serial data output for the configuration interface.
SMPL_CLKM 43 DI Connect SMPL_CLKM to GND for a single-ended ADC sampling clock input. SMPL_CLKM is the negative input for the differential sampling clock input to the ADC.
SMPL_CLKP 44 DI Single-ended ADC sampling clock input. SMPL_CLKP is the positive input for the differential sampling clock input to the ADC.
SMPL_SYNC 45 DI Synchronization input. See the Synchronizing Multiple ADCs section on how to use the SMPL_SYNC pin.
SPI_EN 24 DI Logic input to enable the SPI interface configuration (CS, SCLK, SDI, and SDO). SPI_EN has an internal 100kΩ pullup resistor to the digital interface supply.
VDD_1V8 21, 22, 47, 48, 49 P 1.8V power-supply. Connect 1µF and 0.1µF decoupling capacitors to GND.
Thermal pad — P Exposed thermal pad; connect to GND.
(1) I = input, O = output, I/O = input or output, G = ground, and P = power.