JAJSOT7 March   2023 AMC1306M25E

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagrams
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Digital Output
        1. 7.3.4.1 Output Behavior in Case of a Full-Scale Input
        2. 7.3.4.2 Output Behavior in Case of Input Common-Mode Overrange
        3. 7.3.4.3 Output Behavior in Case of a Missing High-Side Supply
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Shunt Resistor Sizing
        2. 8.2.2.2 Input Filter Design
        3. 8.2.2.3 Bitstream Filtering
      3. 8.2.3 Application Curve
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.9 Electrical Characteristics

minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, INP = –250 mV to 250 mV, INN = 0 V, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
VCMov Common-mode overvoltage detection level (INP + INN) / 2 to AGND AVDD – 2 V
CIN Single-ended input capacitance INN = AGND 2 pF
CIND Differential input capacitance 1 pF
IIB Input bias current INP = INN = AGND, IIB = IBP + IBN, 
–55℃ ≤ TA ≤ 125℃		 –82 –60 –48 μA
RIN Single-ended input resistance INN = AGND, –55℃ ≤ TA ≤ 125℃ 19 kΩ
RIND Differential input resistance –55℃ ≤ TA ≤ 125℃ 22 kΩ
IIO Input offset current ±5 nA
CMTI Common-mode transient immunity 100 150 kV/μs
CMRR Common-mode rejection ratio INP = INN, fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max		 –95 dB
INP = INN, fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max		 –95
BW Input bandwidth 900 kHz
DC ACCURACY
DNL Differential nonlinearity Resolution: 16 bits, 
–55℃ ≤ TA ≤ 125℃		 –0.99 0.99 LSB
INL Integral nonlinearity(2) Resolution: 16 bits, 
–55℃ ≤ TA ≤ 125℃		 –4 ±1 4 LSB
EO Offset error(1)
INP = INN = AGND, TA = 25°C		 –100 ±4.5 100 µV
INP = INN = AGND, TA = –55°C –180 ±20 180
TCEO Offset error temperature drift(3) –1 1 µV/°C
EG Gain error TA = 25°C –0.2% ±0.005% 0.2%
TA = –55°C –0.52% ±0.17% 0.52%
TCEG Gain error temperature drift(4) –40℃ ≤ TA ≤ 125℃ –40 ±20 40 ppm/°C
PSRR Power-supply rejection ratio INP = INN = AGND,
AVDD from 3.0 V to 5.5 V, at DC		 –103 dB
INP = INN = AGND,
AVDD from 3.0 V to 5.5 V,
10-kHz / 100-mV ripple		 –92
AC ACCURACY
SNR Signal-to-noise ratio fIN = 1 kHz 82 86 dB
SINAD Signal-to-noise + distortion fIN = 1 kHz 81.9 85.7 dB
THD Total harmonic distortion(5) 4.5 V ≤ AVDD ≤ 5.5 V, fIN = 1 kHz,
5 MHz ≤ fCLKIN ≤ 21 MHz		 –98 –86 dB
3.0 V ≤ AVDD ≤ 3.6 V, fIN = 1 kHz,
5 MHz ≤ fCLKIN ≤ 20 MHz		 –93 –85
SFDR Spurious-free dynamic range fIN = 1 kHz 83 100 dB
CMOS LOGIC WITH SCHMITT-TRIGGER
IIN Input current DGND ≤ VIN ≤ DVDD 0 7 μA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × DVDD V
CLOAD Output load capacitance 30 pF
VOH High-level output voltage IOH = –4 mA, –55℃ ≤ TA ≤ 125℃ DVDD – 0.4 V
VOL Low-level output voltage IOL = 4 mA, –55℃ ≤ TA ≤ 125℃ 0.4 V
POWER SUPPLY
IAVDD High-side supply current 3.0 V ≤ AVDD ≤ 3.6 V 6.3 8.5 mA
4.5 V ≤ AVDD ≤ 5.5 V 7.2 9.8
IDVDD Low-side supply current 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF		 3.3 4.8 mA
4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF		 3.9 6.0
AVDDUV High-side undervoltage detection threshold AVDD rising, –55℃ ≤ TA ≤ 125℃ 2.45 2.7 2.9 V
AVDD falling, –55℃ ≤ TA ≤ 125℃ 2.4 2.6 2.8
DVDDUV Low-side undervoltage detection threshold DVDD rising, –55℃ ≤ TA ≤ 125℃ 2.2 2.45 2.65 V
DVDD falling, –55℃ ≤ TA ≤ 125℃ 1.75 2.0 2.2
(1) This parameter is input referred.
(2) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer
function expressed as number of LSBs or as a percent of the specified linear full-scale range FSR.
(3) Offset error temperature drift is calculated using the box method, as described by the following equation:
TCEO = (EO,MAX – EO,MIN) / TempRange where EO,MAX and EO,MIN refer to the maximum and minimum EO values measured within the temperature range (–40 to 125℃).
(4) Gain error temperature drift is calculated using the box method, as described by the following equation:
TCEG (ppm) = ((EG,MAX - EG,MIN) / TempRange) x 104 where EG,MAX and EG,MIN refer to the maximum and minimum EG values (in %) measured within the temperature range (–40 to 125℃).
(5) THD is the ratio of the rms sum of the amplitudes of first five higher harmonics to the amplitude of the fundamental.