JAJSEW3C may   2017  – january 2022 AWR1443

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 説明
  5. 4 機能ブロック図
  6. 5 Revision History
  7. 6 Device Comparison
    1. 6.1 Related Products
  8. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Signal Descriptions
    3. 7.3 Pin Multiplexing
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Power-On Hours (POH)
    4. 8.4 Recommended Operating Conditions
    5. 8.5 Power Supply Specifications
    6. 8.6 Power Consumption Summary
    7. 8.7 RF Specification
    8. 8.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 8.9 Timing and Switching Characteristics
      1. 8.9.1  Power Supply Sequencing and Reset Timing
      2. 8.9.2  Synchronized Frame Triggering
      3. 8.9.3  Input Clocks and Oscillators
        1. 8.9.3.1 Clock Specifications
      4. 8.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.9.4.1 Peripheral Description
        2. 8.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. 8.9.4.2.1 SPI Timing Conditions
          2. 8.9.4.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-236 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-237 #GUID-C70CFB1F-161A-495B-85B8-62E1C643D037/T4362547-238
          3. 8.9.4.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input) #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-244 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-245 #GUID-F724BCC6-8F26-42C4-8723-451EDE9A36D3/T4362547-246
        3. 8.9.4.3 SPI Peripheral Mode I/O Timings
          1. 8.9.4.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-70 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-71 #GUID-1B5DE4C6-14B2-48EF-965D-3B03E1AE325B/T4362547-73
        4. 8.9.4.4 Typical Interface Protocol Diagram (Peripheral Mode)
      5. 8.9.5  LVDS Interface Configuration
        1. 8.9.5.1 LVDS Interface Timings
      6. 8.9.6  General-Purpose Input/Output
        1. 8.9.6.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 8.9.7  Controller Area Network Interface (DCAN)
        1. 8.9.7.1 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 8.9.8  Serial Communication Interface (SCI)
        1. 8.9.8.1 SCI Timing Requirements
      9. 8.9.9  Inter-Integrated Circuit Interface (I2C)
        1. 8.9.9.1 I2C Timing Requirements #GUID-36963FBF-DA1A-4FF8-B71D-4A185830E708/T4362547-185
      10. 8.9.10 Quad Serial Peripheral Interface (QSPI)
        1. 8.9.10.1 QSPI Timing Conditions
        2. 8.9.10.2 Timing Requirements for QSPI Input (Read) Timings #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-210 #GUID-6DC69BBB-F187-4499-AC42-8C006552DEE1/T4362547-209
        3. 8.9.10.3 QSPI Switching Characteristics
      11. 8.9.11 JTAG Interface
        1. 8.9.11.1 JTAG Timing Conditions
        2. 8.9.11.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.9.11.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 External Interfaces
    4. 9.4 Subsystems
      1. 9.4.1 RF and Analog Subsystem
        1. 9.4.1.1 Clock Subsystem
        2. 9.4.1.2 Transmit Subsystem
        3. 9.4.1.3 Receive Subsystem
        4. 9.4.1.4 Radio Processor Subsystem
      2. 9.4.2 Main (Control) System
      3. 9.4.3 Host Interface
    5. 9.5 Accelerators and Coprocessors
    6. 9.6 Other Subsystems
      1. 9.6.1 ADC Channels (Service) for User Application
        1. 9.6.1.1 GP-ADC Parameter
    7. 9.7 Boot Modes
      1. 9.7.1 Flashing Mode
      2. 9.7.2 Functional Mode
  11. 10Applications, Implementation, and Layout
    1. 10.1 Application Information
    2. 10.2 Short-Range Radar
    3. 10.3 Blind Spot Detector and Ultrasonic Upgrades
    4. 10.4 Reference Schematic
  12. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • ABL|161
サーマルパッド・メカニカル・データ
発注情報

7.2.1 Signal Descriptions

FUNCTIONSIGNAL NAMEPIN NUMBERPIN TYPEDEFAULT PULL STATUS(1)DESCRIPTION
TransmittersTX1B4O—Single-ended transmitter1 o/p
TX2B6O—Single-ended transmitter2 o/p
TX3B8O—Single-ended transmitter3 o/p
ReceiversRX1M2I—Single-ended receiver1 i/p
RX2K2I—Single-ended receiver2 i/p
RX3H2I—Single-ended receiver3 i/p
RX4F2I—Single-ended receiver4 i/p
LVDS TXLVDS_TXP[0]G15O—Differential data Out – Lane 0
LVDS_TXM[0]G14O—
LVDS_CLKPJ15O—Differential clock Out
LVDS_CLKMJ14O—
LVDS_TXP[1]H15O—Differential data Out – Lane 1
LVDS_TXM[1]H14O—
HS_RESERVED_TXP[2]K15O—Differential data Out – Lane 2
HS_RESERVED_TXM[2]K14O—
HS_RESERVED_TXP[3]L15O—Differential data Out – Lane 3
HS_RESERVED_TXM[3]L14O—
LVDS_FRCLKPM15O—Differential debug port 1
LVDS_FRCLKMM14O—
HS_DEBUG2_PN15O—Differential debug port 2
HS_DEBUG2_MN14O—
RESERVEDB1, B15, D1, D15—
Reference clockOSC_CLKOUTA14O—Reference clock output from clocking subsystem after cleanup PLL. Can be used by peripheral chip in multichip cascading
System synchronizationSYNC_OUTP11OPull DownLow-frequency frame synchronization signal output. Can be used by peripheral chip in multichip cascading
SYNC_INN10IPull DownLow-frequency frame synchronization signal input.
This signal could also be used as a hardware trigger for frame start
SPI control interface from external MCU (default peripheral mode)SPI_CS_1R7IPull UpSPI chip select
SPI_CLK_1R9IPull DownSPI clock
MOSI_1R8IPull UpSPI data input
MISO_1P5OPull UpSPI data output
SPI_HOST_INTR_1P6OPull DownSPI interrupt to host
RESERVEDR3, R4, R5, P4—
ResetNRESETP12I—Power on reset for chip. Active low
WARM_RESETN12IOOpen DrainOpen-drain fail-safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.
SafetyNERROR_OUTN8OOpen DrainOpen-drain fail-safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.
NERROR_INP7IOpen DrainFail-safe input to the device. Error output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by firmware
JTAGTMSL13IPull UpJTAG port for standard boundary scan
TCKM13IPull Down
TDIH13IPull Up
TDOJ13O—
Reference oscillatorCLKPE14I—In XTAL mode: Input for the reference crystal
In External clock mode: Single ended input reference clock port
CLKMF14O— In XTAL mode: Feedback drive for the reference crystal
In External clock mode: Connect this port to ground
Band-gap voltageVBGAPB10O—
Power supplyVDDINF13,N11,P15,R6POW—1.2-V digital power supply
VIN_SRAMR14POW—1.2-V power rail for internal SRAM
VNWAP14POW—1.2-V power rail for SRAM array back bias
VIOINR13POW—I/O supply (3.3-V or 1.8-V): All CMOS I/Os would operate on this supply.
VIOIN_18K13POW—1.8-V supply for CMOS IO
VIN_18CLKB11POW—1.8-V supply for clock module
VIOIN_18DIFFD13POW—1.8-V supply for high speed interface port
ReservedG13POW—No connect
VIN_13RF1G5,J5,H5POW—1.3-V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board
VIN_13RF2C2,D2POW—
VIN_18BBK5,F5POW—1.8-V Analog baseband power supply
VIN_18VCOB12POW—1.8-V RF VCO supply
VSSE5,E6,E8,E10,E11,F9,F11,G6,G7,G8,G10,H7,H9,H11,J6,J7,J8,J10,K7,K8,K9,K10,K11,L5,L6,L8,L10,R15GND—Digital ground
VSSAA1,A3,A5,A7,A9,A15,B3,B5,B7,B9,B13,B14,C1,C3,C4,C5,C6,C7,C8,C9,C15,E1,E2,E3,E13,E15,F3,G1,G2,G3,H3,J1,J2,J3,K3,L1,L2,L3, M3,N1,N2,N3,R1GND—Analog ground
Internal LDO output/inputsVOUT_14APLLA10O—
VOUT_14SYNTHA13O—
VOUT_PAA2,B2O—
External clock outPMIC_CLK_OUTP13O—Dithered clock input to PMIC
MCU_CLK_OUTN9O—Programmable clock given out to external MCU or the processor
General-purpose I/OsGPIO[0]N4IOPull DownGeneral-purpose IO
GPIO[1]N7IOPull DownGeneral-purpose IO
GPIO[2]N13IOPull DownGeneral-purpose IO
QSPI for Serial Flash(2)QSPI_CSP8OPull UpChip-select output from the device. Device is a controller connected to serial flash peripheral.
QSPI_CLKR10OPull DownClock output from the device. Device is a controller connected to serial flash peripheral.
QSPI[0]R11IOPull DownData IN/OUT
QSPI[1]P9IOPull DownData IN/OUT
QSPI[2]R12IOPull UpData IN/OUT
QSPI[3]P10IOPull UpData IN/OUT
Flash programming and RS232 UART(2)RS232_TXN6OPull DownUART pins for programming external flash in preproduction/debug hardware.
RS232_RXN5IPull Up
Test and Debug output for preproduction phase. Can be pinned out on production hardware for field debugAnalog Test1 / GPADC1P1IO—GP ADC channel 1
Analog Test2 / GPADC2P2IO—GP ADC channel 2
Analog Test3 / GPADC3P3IO—GP ADC channel 3
Analog Test4 R2IO—GP ADC channel 4
ANAMUX / GPADC5C13IO—GP ADC channel 5
VSENSE / GPADC6C14IO—GP ADC channel 6
(1) Status of PULL structures associated with the IO after device POWER UP.
(2) This option is for development/debug in preproduction phase. Can be disabled by firmware pin mux setting.