JAJSOY8H November   2011  – July 2022 BQ24160 , BQ24160A , BQ24161 , BQ24161B , BQ24163 , BQ24168

PRODUCTION DATA  

  1. 特長
  2. アプリケーション
  3. 概要
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Charge Mode Operation
        1. 8.3.1.1 Charge Profile
        2. 8.3.1.2 PWM Controller in Charge Mode
      2. 8.3.2  Battery Charging Process
      3. 8.3.3  Battery Detection
      4. 8.3.4  Dynamic Power Path Management (DPPM)
      5. 8.3.5  Input Source Connected
      6. 8.3.6  Battery Only Connected
      7. 8.3.7  Battery Discharge FET (BGATE)
      8. 8.3.8  DEFAULT Mode
      9. 8.3.9  Safety Timer and Watchdog Timer (BQ24160/BQ24161/BQ24161B/BQ24163 only)
      10. 8.3.10 D+, D– Based Adapter Detection for the USB Input (D+, D–, BQ24160/0A/3)
      11. 8.3.11 USB Input Current Limit Selector Input (PSEL, BQ24161/161B/168 only)
      12. 8.3.12 Hardware Chip Disable Input (CD)
      13. 8.3.13 LDO Output (DRV)
      14. 8.3.14 External NTC Monitoring (TS)
      15. 8.3.15 Thermal Regulation and Protection
      16. 8.3.16 Input Voltage Protection in Charge Mode
        1. 8.3.16.1 Sleep Mode
        2. 8.3.16.2 Input Voltage Based DPM
        3. 8.3.16.3 Bad Source Detection
        4. 8.3.16.4 Input Overvoltage Protection
        5. 8.3.16.5 Reverse Boost (Boost Back) Prevention Circuit
      17. 8.3.17 Charge Status Outputs (STAT, INT)
      18. 8.3.18 Good Battery Monitor
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Serial Interface Description
        1. 8.5.1.1 F/S Mode Protocol
    6. 8.6 Register Maps
      1. 8.6.1 Status/Control Register (READ/WRITE)
      2. 8.6.2 Battery/ Supply Status Register (READ/WRITE)
      3. 8.6.3 Control Register (READ/WRITE)
      4. 8.6.4 Control/Battery Voltage Register (READ/WRITE)
      5. 8.6.5 Vender/Part/Revision Register (READ only)
      6. 8.6.6 Battery Termination/Fast Charge Current Register (READ/WRITE)
      7. 8.6.7 VIN-DPM Voltage/ DPPM Status Register
      8. 8.6.8 Safety Timer/ NTC Monitor Register (READ/WRITE)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Output Inductor and Capacitor Selection Guidelines
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Requirements for SYS Output
    2. 10.2 Requirements for Charging
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
      1.      Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Battery Charging Process

Assuming a vaild input source is attached to IN or USB, as soon as a deeply discharged or shorted battery is attached to the BAT pin, (VBAT < VBATSHRT), the BQ2416xx applies IBATSHRT to close the pack protector switch and bring the battery voltage up to acceptable charging levels. During this time, the battery FET is linearly regulated and the system output is regulated to VSYS(REG). Once the battery rises above VBATSHRT, the charge current is regulated to the value set in the I2C register. The battery FET is linearly regulated to maintain the system voltage at VSYS(REG). Under normal conditions, the time spent in this region is a very short percentage of the total charging time, so the linear regulation of the charge current does not affect the overall charging efficiency for very long. If the die temperature does rise, the thermal regulation circuit reduces the charge current to maintain a die temperature less than 120°C. If the current limit for the SYS output is reached (limited by the input current limit, or VIN_DPM), the SYS output drops to the VMINSYS output voltage. When this happens, the charge current is reduced to provide the system with all the current that is needed while maintaining the minimum system voltage. If the charge current is reduced to 0mA, pulling further current from SYS causes the output to fall to the battery voltage and enter supplement mode. (See the Dynamic Power Path Management section for more details.)

Once the battery is charged enough so that the system voltage begins to rise above VSYS(REG), the battery FET is turned on fully and the battery is charged with the full programmed charge current set by the I2C interface, ICHARGE. The slew rate for the fast-charge current is controlled to minimize current and voltage overshoot during transients. The charge current is regulated to ICHARGE until the battery is charged to the regulation voltage. As the battery voltage rises above VRCH, the battery regulation loop is activated. This may result in a small step down in the charge current as the loops transition between the charge current and charge voltage loops. As the battery voltage charges up to the regulation voltage, VBATREG, the charge current is tapered down as shown in Figure 8-1 while the SYS output remains connected to the battery. The voltage between the BAT and PGND pins is regulated to VBATREG. The BQ2416xx is a fixed single-cell voltage version, with adjustable regulation voltage (3.5 V to 4.44 V), programmed using the I2C interface.

The BQ2416xx monitors the charging current during the voltage-regulation phase. If the battery voltage is above the recharge threshold and the charge current has naturally tapered down to and remains below termination threshold, ITERM, (without disturbance from events like supplement mode) for 32 ms, the charger terminates charge, turns off the battery charging FET and enters battery detection. Termination is disabled when the charge current is reduced by a loop other than the voltage regulation loop or the input current limit is set to 100 mA. For example, when the BQ2416xx is in half charge due to TS function, reverse boost protection is active, LOW_CHG bit is set, or the thermal regulation, VINDPM or input current loops are active, termination will not occur. This prevents false termination events. During termination, the system output is regulated to the VSYS(REG) and supports the full current available from the input and the battery supplement mode is available. (See the Dynamic Power Path Management section for more details.) The termination current level is programmable. When setting the termination threshold less than 150mA, the reverse boost protection may trip falsely with load transients and very fully charged batteries. This will prevent termination while in the reverse boost protection and may extend charge time. To disable the charge current termination, the host sets the charge termination bit (TE) of charge control register to 0, refer to I2C section for details.

A new charge cycle is initiated if CD is low when either

  1. VSUPPLY rises above UVLO while a battery with VBAT < VBATREG - VRCH is attached or
  2. a battery with VBAT < VBATREG - VRCH is attached while VSUPPLY is above UVLO.

With VSUPPLY above UVLO and V(BAT) < VBOVP, a recharge cycle is initiated when one of the following conditions is detected:

  1. The battery voltage falls below the VBAT(REG)-VRCH threshold.
  2. CE bit toggle or RESET bit toggle
  3. Supplement mode event occurs
  4. CD pin or HI-Z bit toggle

VBAT(REG) should never be programmed less than VBAT. If the battery is ever 5% above the regulation threshold, the battery OVP circuit shuts the PWM converter off immediately and the battery FET is turned on to discharge the battery to safe operating levels. If the battery OVP condition exists for the 1ms deglitch, a battery OVP fault is reported in the I2C status registers. The battery OVP fault is cleared when the battery voltage discharges below VRCH or if the IC enters hi-impedance mode (HZ_MODE=1 or CD=1). Always write BQ2416xx to high impedance mode before changing VBATREG to clear BOVP condition to ensure proper operation.

If the battery voltage is ever greater than VBATREG (for example, when an almost fully charged battery enters the JEITA WARM state due to the TS pin) but less than VBOVP, the reverse boost protection circuitry may activate as explained later in this data sheet. If the battery is ever above VBOVP, the buck converter turns off and the internal battery FET is turned on. This prevents further overcharging of the battery and allows the battery to discharge to safe operating levels. The battery OVP event does not clear until the battery voltage falls below VRCH.