SLUSBI4B April   2013  – December 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Device Power Up
        1. 8.3.1.1 Power-On-Reset (POR)
        2. 8.3.1.2 Power Up from Battery without DC Source
          1. 8.3.1.2.1 BATFET Turn Off
          2. 8.3.1.2.2 Shipping Mode
        3. 8.3.1.3 Power Up from DC Source
          1. 8.3.1.3.1 REGN LDO
          2. 8.3.1.3.2 Input Source Qualification
          3. 8.3.1.3.3 Input Current Limit Detection
          4. 8.3.1.3.4 PSEL/OTG Pins Set Input Current Limit
          5. 8.3.1.3.5 HIZ State wth 100mA USB Host
          6. 8.3.1.3.6 Force Input Current Limit Detection
        4. 8.3.1.4 Converter Power-Up
        5. 8.3.1.5 Boost Mode Operation from Battery
      2. 8.3.2 Power Path Management
        1. 8.3.2.1 Narrow VDC Architecture
        2. 8.3.2.2 Dynamic Power Management
        3. 8.3.2.3 Supplement Mode
      3. 8.3.3 Battery Charging Management
        1. 8.3.3.1 Autonomous Charging Cycle
        2. 8.3.3.2 Battery Charging Profile
        3. 8.3.3.3 Battery Path Impedance IR Compensation
        4. 8.3.3.4 Thermistor Qualification
          1. 8.3.3.4.1 Cold/Hot Temperature Window
        5. 8.3.3.5 Charging Termination
          1. 8.3.3.5.1 Termination when FORCE_20PCT (REG02[0]) = 1
          2. 8.3.3.5.2 Termination when TERM_STAT (REG05[6]) = 1
        6. 8.3.3.6 Charging Safety Timer
        7. 8.3.3.7 USB Timer when Charging from USB100mA Source
      4. 8.3.4 Status Outputs (PG, STAT, and INT)
        1. 8.3.4.1 Power Good Indicator (PG)
        2. 8.3.4.2 Charging Status Indicator (STAT)
        3. 8.3.4.3 Interrupt to Host (INT)
      5. 8.3.5 Protections
        1. 8.3.5.1 Input Current Limit on ILIM
        2. 8.3.5.2 Thermal Regulation and Thermal Shutdown
        3. 8.3.5.3 Voltage and Current Monitoring in Buck Mode
          1. 8.3.5.3.1 Input Overvoltage (ACOV)
          2. 8.3.5.3.2 System Overvoltage Protection (SYSOVP)
        4. 8.3.5.4 Overcurrent Protection in Boost Mode
          1. 8.3.5.4.1 VBUS Overvoltage Protection in Boost Mode
        5. 8.3.5.5 Battery Protection
          1. 8.3.5.5.1 Battery Overcurrent Protection (BATOVP)
          2. 8.3.5.5.2 Charging During Battery Short Protection
          3. 8.3.5.5.3 System Overcurrent Protection
      6. 8.3.6 Serial Interface
        1. 8.3.6.1 Data Validity
        2. 8.3.6.2 START and STOP Conditions
        3. 8.3.6.3 Byte Format
        4. 8.3.6.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.3.6.5 Slave Address and Data Direction Bit
          1. 8.3.6.5.1 Single Read and Write
          2. 8.3.6.5.2 Multi-Read and Multi-Write
    4. 8.4 Device Functional Modes
      1. 8.4.1 Host Mode and Default Mode
        1. 8.4.1.1 Plug in USB 100mA Source with Good Battery
        2. 8.4.1.2 USB Timer when Charging from USB100mA Source
    5. 8.5 Register Map
      1. 8.5.1 I2C Registers
        1. 8.5.1.1  Input Source Control Register REG00 (reset = 00111000, or 3D)
        2. 8.5.1.2  Power-On Configuration Register REG01 (reset = 00011011, or 1B)
        3. 8.5.1.3  Charge Current Control Register REG02 (reset = 00100000, or 20)
        4. 8.5.1.4  Pre-Charge/Termination Current Control Register REG 03 (reset = 00010001, or 11)
        5. 8.5.1.5  Charge Voltage Control Register REG04 (reset = 10011010, or 9A)
        6. 8.5.1.6  Charge Termination/Timer Control Register REG05 (reset = 10011010, or 9A)
        7. 8.5.1.7  IR Compensation / Thermal Regulation Control Register REG06 (reset = 00000011, or 03)
        8. 8.5.1.8  Misc Operation Control Register REG07 (reset = 01001011, or 4B)
        9. 8.5.1.9  System Status Register REG08
        10. 8.5.1.10 Fault Register REG09
        11. 8.5.1.11 Vender / Part / Revision Status Register REG0A
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Input Capacitor
        3. 9.2.2.3 Output Capacitor
      3. 9.2.3 Application Performance Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

A typical application consists of the device configured as an I2C controlled power path management device and a single cell Li-Ion battery charger for single cell Li-Ion and Li-polymer batteries used in a wide range of tablets and other portable devices. It integrates an input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2), low-side switching FET (LSFET, Q3), and BATFET (Q4) between the system and battery. The device also integrates a bootstrap diode for the high-side gate drive.

9.2 Typical Application

Typical applications are shown in Figure 36 and Figure 37.

bq24292i App_Diagram3_slusbe1.gif
VREF is the pull up voltage of I2C communication interface.
Figure 36. bq24292i with PSEL, USB On-The-Go (OTG), No Thermistor Connections
bq24292i Bq24292i_application_diagram_SLUSBI4.gif
VREF is the pull up voltage of I2C communication interface.
Figure 37. bq24292i with PSEL, Charging from 5V USB, and Two Thermistor Connections

9.2.1 Design Requirements

The design parameters are listed in the following table.

Table 18. Design Parameters

DESIGN PARAMETER EXAMPLE VALUE
Input voltage 3.9 V - 17 V
Input current limit 3A
Fast charge current 4A
Boost mode output current 1.3A

9.2.2 Detailed Design Procedure

9.2.2.1 Inductor Selection

The device has 1.5 MHz switching frequency to allow the use of small inductor and capacitor values. The Inductor saturation current should be higher than the charging current (ICHG) plus half the ripple current (IRIPPLE):

Equation 5. bq24292i Eq5_slusaw5.gif

The inductor ripple current depends on input voltage (VBUS), duty cycle (D = VBAT/VVBUS), switching frequency (fs) and inductance (L):

Equation 6. bq24292i Eq6_slusaw5.gif

The maximum inductor ripple current happens with D = 0.5 or close to 0.5. Usually inductor ripple is designed in the range of (20–40%) maximum charging current as a trade-off between inductor size and efficiency for a practical design. Typical inductor value is 2.2µH.

9.2.2.2 Input Capacitor

Input capacitor should have enough ripple current rating to absorb input switching ripple current. The worst case RMS ripple current is half of the charging current when duty cycle is 0.5. If the converter does not operate at 50% duty cycle, then the worst case capacitor RMS current ICIN occurs where the duty cycle is closest to 50% and can be estimated by the following equation:

Equation 7. bq24292i Eq7_slusaw5.gif

For best performance, VBUS should be decouple to PGND with 1μF capacitance. The remaining input capacitor should be place on PMID.

Low ESR ceramic capacitor such as X7R or X5R is preferred for input decoupling capacitor and should be placed to the drain of the high side MOSFET and source of the low side MOSFET as close as possible. Voltage rating of the capacitor must be higher than normal input voltage level. 25V rating or higher capacitor is preferred for 15V input voltage.

9.2.2.3 Output Capacitor

Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The output capacitor RMS current ICOUT is given:

Equation 8. bq24292i Eq8_slusaw5.gif

The output capacitor voltage ripple can be calculated as follows:

Equation 9. bq24292i Eq9_slusaw5.gif

At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the output filter LC.

The charger device has internal loop compensator. To get good loop stability, the resonant frequency of the output inductor and output capacitor should be designed between 15 kHz and 36 kHz. The preferred ceramic capacitor is 6V or higher rating, X7R or X5R.

9.2.3 Application Performance Curves

bq24292i SCOPE1_SLUSAW5A.gif
VBAT 3.2 V
Figure 38. Power Up from USB100mA
bq24292i SCOPE3_SLUSAW5A.gif
Figure 40. Power Up with Charge Enabled
bq24292i SCOPE5_SLUSAW5A.gif
VBUS 12 V
Figure 42. Charge Disable
bq24292i SCOPE7_SLUSAW5A.gif
VBUS 9 V, IIN 1.5 A, VBAT 3.8 V
Figure 44. Load Transient during Supplement Mode
bq24292i SCOPE9_SLUSAW5A.gif
VBUS 9 V, No Battery, ISYS 10 mA, Charge Disable
Figure 46. PFM Switching Waveform
bq24292i SCOPE10_SLUSAW5A.gif
VBAT 3.8 V, ILOAD 1 A
Figure 48. Boost Mode Switching Waveform
bq24292i SCOPE13_SLUSBI4.gif
2-Ω Load at VBUS
Figure 50. Boost Mode Hiccup Mode Overcurrent Protection
bq24292i SCOPE2_SLUSAW5A.gif
VBAT 3.2 V
Figure 39. Power Up with Charge Disabled
bq24292i SCOPE4_SLUSAW5A.gif
VBUS 5 V
Figure 41. Charge Enable
bq24292i SCOPE6_SLUSAW5A.gif
VBUS 5 V, IIN 3 A, Charge Disable
Figure 43. Input Current DPM Response without Battery
bq24292i SCOPE8_SLUSAW5A.gif
VBUS 12 V, VBAT 3.8 V, ICHG 3 A
Figure 45. PWM Switching Waveform
bq24292i SCOPE12_SLUSBI4.gif
5-Ω Load at VBUS
Figure 47. Boost Mode Enable
bq24292i SCOPE11_SLUSAW5A.gif
VBAT 3.8 V
Figure 49. Boost Mode Load Transient