SLUS763D July   2007  – April 2016

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Power Down
      2. 7.3.2 Power-On Reset
      3. 7.3.3 Operation
        1. 7.3.3.1 Input Overvoltage Protection
        2. 7.3.3.2 Input Overcurrent Protection
        3. 7.3.3.3 Battery Overvoltage Protection
        4. 7.3.3.4 Thermal Protection
        5. 7.3.3.5 Enable Function
        6. 7.3.3.6 Fault Indication
    4. 7.4 Device Functional Modes
      1. 7.4.1 OPERATION Mode
      2. 7.4.2 POWER-DOWN Mode
      3. 7.4.3 POWER-ON RESET Mode
  8. 8 Applications and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Selection of RBAT
        2. 8.2.2.2 Selection of RCE, RFAULT, and RPU
        3. 8.2.2.3 Selection of Input and Output Bypass Capacitors
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
    1. 9.1 Powering Accessories
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Related Links
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DSJ|12
  • DSG|8
サーマルパッド・メカニカル・データ
発注情報

7 Detailed Description

7.1 Overview

The bq24314 and bq24316 devices monitor the input voltage, input current, and the battery voltage to protect the charging system of a Li-Ion battery. The protection features can be enabled through the /CE pin.

When enabled, the system is protected against input overvoltage by turning off an internal switch, immediately removing power from the charging circuit. The system is protected against an overcurrent condition by limiting the input current to a safe value for a blanking duration before disconnecting the input from the output by turning the switch off. The overcurrent threshold is user-programmable. Additionally, the device also monitors its own die temperature and switches off if it becomes too hot.

7.2 Functional Block Diagram

bq24314 bq24316 sim_bd_lus763.gif

7.3 Feature Description

7.3.1 Power Down

The device remains in power-down mode when the input voltage at the IN pin is below the undervoltage threshold VUVLO. The FET Q1 connected between IN and OUT pins is off, and the status output, FAULT, is set to Hi-Z.

7.3.2 Power-On Reset

The device resets when the input voltage at the IN pin exceeds the UVLO threshold. All internal counters and other circuit blocks are reset. The IC then waits for duration tDGL(PGOOD) for the input voltage to stabilize. If, after tDGL(PGOOD), the input voltage and battery voltage are safe, FET Q1 is turned ON. The IC has a soft-start feature to control the inrush current. The soft-start minimizes the ringing at the input (the ringing occurs because the parasitic inductance of the adapter cable and the input bypass capacitor form a resonant circuit). Figure 12 shows the power-up behavior of the device. Because of the deglitch time at power-on, if the input voltage rises rapidly to beyond the OVP threshold, the device will not switch on at all, instead it will go into protection mode and indicate a fault on the FAULT pin, as shown in Figure 13.

7.3.3 Operation

The device continuously monitors the input voltage, the input current, and the battery voltage as described in detail in the following sections.

7.3.3.1 Input Overvoltage Protection

If the input voltage rises above VOVP, the internal FET Q1 is turned off, removing power from the circuit. As shown in Figure 14 to Figure 17, the response is very rapid, with the FET turning off in less than a microsecond. The FAULT pin is driven low. When the input voltage returns below VOVP – VHYS-OVP (but is still above VUVLO), the FET Q1 is turned on again after a deglitch time of tON(OVP) to ensure that the input supply has stabilized. Figure 18 shows the recovery from input OVP.

7.3.3.2 Input Overcurrent Protection

The overcurrent threshold is programmed by a resistor RILIM connected from the ILIM pin to VSS. Figure 5 shows the OCP threshold as a function of RILIM, and may be approximated by Equation 1:

Equation 1. IOCP = 25 ÷ RILIM

where

  • current is in A
  • and resistance is in kΩ

If the load current tries to exceed the IOCP threshold, the device limits the current for a blanking duration of tBLANK(OCP). If the load current returns to less than IOCP before tBLANK(OCP) times out, the device continues to operate. However, if the overcurrent situation persists for tBLANK(OCP), the FET Q1 is turned off for a duration of tREC(OCP), and the FAULT pin is driven low. The FET is then turned on again after tREC(OCP) and the current is monitored all over again. Each time an OCP fault occurs, an internal counter is incremented. If 15 OCP faults occur in one charge cycle, the FET is turned off permanently. The counter is cleared either by removing and re-applying input power, or by disabling and re-enabling the device with the CE pin. Figure 19 to Figure 21 show what happens in an overcurrent fault.

To prevent the input voltage from spiking up due to the inductance of the input cable, Q1 is turned off slowly, resulting in a soft-stop, as shown in Figure 21.

7.3.3.3 Battery Overvoltage Protection

The battery overvoltage threshold BVOVP is internally set to 4.35 V. If the battery voltage exceeds the BVOVP threshold, the FET Q1 is turned off, and the FAULT pin is driven low. The FET is turned back on once the battery voltage drops to BVOVP – VHYS-BOVP (see Figure 22 and Figure 23). Each time a battery overvoltage fault occurs, an internal counter is incremented. If 15 such faults occur in one charge cycle, the FET is turned off permanently. The counter is cleared either by removing and re-applying input power, or by disabling and re-enabling the device with the CE pin. In the case of a battery overvoltage fault, Q1 is switched OFF gradually (see Figure 22).

7.3.3.4 Thermal Protection

If the junction temperature of the device exceeds TJ(OFF), the FET Q1 is turned off, and the FAULT pin is driven low. The FET is turned back on when the junction temperature falls below TJ(OFF) – TJ(OFF-HYS).

7.3.3.5 Enable Function

The IC has an enable pin which can be used to enable or disable the device. When the CE pin is driven high, the internal FET is turned off. When the CE pin is low, the FET is turned on if other conditions are safe. The OCP counter and the Bat-OVP counter are both reset when the device is disabled and re-enabled. The CE pin has an internal pulldown resistor and can be left floating.

NOTE

The FAULT pin functionality is also disabled when the CE pin is high.

7.3.3.6 Fault Indication

The FAULT pin is an active-low open-drain output. It is in a high-impedance state when operating conditions are safe, or when the device is disabled by setting CE high. With CE low, the FAULT pin goes low whenever any of these events occurs:

  • Input overvoltage
  • Input overcurrent
  • Battery overvoltage
  • IC Overtemperature
bq24314 bq24316 flo_cht_lus763.gif Figure 10. Flow Diagram

7.4 Device Functional Modes

7.4.1 OPERATION Mode

The bq2431x device continuously monitors the input voltage, the input current, and the battery voltage. As long as the input voltage is less than VOVP, the output voltage tracks the input voltage (less the drop caused by RDSON of Q1). During fault conditions, the internal FET is turned off and the output is isolated from the input source.

7.4.2 POWER-DOWN Mode

The device remains in POWER-DOWN mode when the input voltage at the IN pin is below the undervoltage lock-out threshold, VUVLO. The FET Q1 (see Functional Block Diagram) connected between IN and OUT pins is off. See Figure 10.

7.4.3 POWER-ON RESET Mode

The device resets all internal timers when the input voltage at the IN pin exceeds the UVLO threshold. The gate driver for the external P-FET is enabled. The device then waits for duration tDGL(PGOOD) for the input voltage to stabilize. If, after tDGL(PGOOD), the input voltage and battery voltage are safe, FET Q1 is turned ON. The device has a soft-start feature to control the inrush current. This soft-start minimizes voltage ringing at the input (the ringing occurs because the parasitic inductance of the adapter cable and the input bypass capacitor form a resonant circuit). Figure 12 shows the power-up behavior of the device. Because of the deglitch time at power-on, if the input voltage rises rapidly to beyond the OVP threshold, the device will not switch on at all, as shown in Figure 13.