JAJSSD2A October   2023  – December 2023 BQ25638

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 概要 (続き)
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-On-Reset (POR)
      2. 7.3.2  Device Power Up from Battery
      3. 7.3.3  Device Power Up from Input Source
        1. 7.3.3.1 REGN LDO Power Up
        2. 7.3.3.2 Poor Source Qualification
        3. 7.3.3.3 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        4. 7.3.3.4 Converter Power-Up
        5. 7.3.3.5 Input Current Optimizer (ICO)
        6. 7.3.3.6 Switching Frequency and Dithering Feature
      4. 7.3.4  Power Path Management
        1. 7.3.4.1 Narrow VDC Architecture
        2. 7.3.4.2 Dynamic Power Management
          1. 7.3.4.2.1 Input Current Limit on ILIM Pin
        3. 7.3.4.3 High Impedance (HIZ) Mode
      5. 7.3.5  Battery Charging Management
        1. 7.3.5.1 Autonomous Charging Cycle
        2. 7.3.5.2 Battery Charging Profile
        3. 7.3.5.3 Charging Termination
        4. 7.3.5.4 Thermistor Qualification
          1. 7.3.5.4.1 Advanced Temperature Profile in Charge Mode
          2. 7.3.5.4.2 TS Pin Thermistor Configuration
          3. 7.3.5.4.3 Cold/Hot Temperature Window in OTG Mode
          4. 7.3.5.4.4 JEITA Charge Rate Scaling
          5. 7.3.5.4.5 TS_BIAS Pin
        5. 7.3.5.5 Charging Safety Timers
      6. 7.3.6  USB On-The-Go (OTG)
        1. 7.3.6.1 Boost OTG Mode
      7. 7.3.7  Integrated 12-bit ADC for Monitoring
      8. 7.3.8  Status Outputs (INT , PG , STAT)
        1. 7.3.8.1 PG Pin Power Good Indicator
        2. 7.3.8.2 Charging Status Indicator (STAT)
        3. 7.3.8.3 Interrupt to Host (INT)
      9. 7.3.9  BATFET Control
        1. 7.3.9.1 Shutdown Mode
        2. 7.3.9.2 Ultra-Low Power Mode
        3. 7.3.9.3 System Power Reset
      10. 7.3.10 Protections
        1. 7.3.10.1 Voltage and Current Monitoring in Battery Only and HIZ Modes
          1. 7.3.10.1.1 Battery Overcurrent Protection
          2. 7.3.10.1.2 Battery Undervoltage Lockout
        2. 7.3.10.2 Voltage and Current Monitoring in Forward Mode
          1. 7.3.10.2.1 Input Overvoltage
          2. 7.3.10.2.2 System Overvoltage Protection (SYSOVP)
          3. 7.3.10.2.3 Forward Converter Cycle-by-Cycle Current Limit
          4. 7.3.10.2.4 System Short
          5. 7.3.10.2.5 Battery Overvoltage Protection (BATOVP)
          6. 7.3.10.2.6 Sleep and Poor Source Comparators
        3. 7.3.10.3 Voltage and Current Monitoring in Reverse Mode
          1. 7.3.10.3.1 Boost Mode Overvoltage Protection
          2. 7.3.10.3.2 Boost Mode Duty Cycle Protection
          3. 7.3.10.3.3 Boost Mode PMID Undervoltage Protection
          4. 7.3.10.3.4 Boost Mode Battery Undervoltage
          5. 7.3.10.3.5 Boost Converter Cycle-by-Cycle Current Limit
          6. 7.3.10.3.6 Boost Mode SYS Short
        4. 7.3.10.4 Thermal Regulation and Thermal Shutdown
          1. 7.3.10.4.1 Thermal Protection in Buck Mode
          2. 7.3.10.4.2 Thermal Protection in Boost Mode
          3. 7.3.10.4.3 Thermal Protection in Battery-only Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host Mode and Default Mode
      2. 7.4.2 Register Bit Reset
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
        1. 7.5.1.1 Data Validity
        2. 7.5.1.2 START and STOP Conditions
        3. 7.5.1.3 Byte Format
        4. 7.5.1.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 7.5.1.5 Target Address and Data Direction Bit
        6. 7.5.1.6 Single Write and Read
        7. 7.5.1.7 Multi-Write and Multi-Read
    6. 7.6 BQ25638 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Inductor Selection
        2. 8.2.2.2 Input Capacitor
        3. 8.2.2.3 Output Capacitor
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 サード・パーティ製品に関する免責事項
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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7.3.8.3 Interrupt to Host (INT)

In many applications, the host does not continually poll the charger status registers. Instead, the INT pin may be used to notify the host of a status change with a 256-μs INT pulse. Upon receiving the interrupt pulse, the host may read the flag registers (Charger_Flag_X and FAULT_Flag_X) to determine the event that caused the interrupt, and for each flagged event, read the corresponding status registers (Charger_Status_X and FAULT_Status_X) to determine the current state. Once set to 1, the flag bits remain latched until they are read by the host, which clears them. The status bits, however, are updated whenever there is a change to status and always represent the current state of the system.

The INT events can be masked off to prevent INT pulses from being sent out when they occur, with the exception of the initial power-up interrupt. Interrupt events are masked by setting their mask bit in registers (Charger_Mask_X and FAULT_Mask_X.) Events always cause the corresponding flag bit to be set to 1, regardless of whether or not the interrupt pulse has been masked.