SLUSCH6B March   2016  – March 2017

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Functional Block Diagram
    2. 8.2 Feature Description
      1. 8.2.1  Device Power-On-Reset (POR)
      2. 8.2.2  Device Power Up from Battery without Input Source
      3. 8.2.3  Device Power Up from Input Source
        1. 8.2.3.1 Power Up REGN Regulation (LDO)
        2. 8.2.3.2 Poor Source Qualification
        3. 8.2.3.3 Input Source Type Detection
          1. 8.2.3.3.1 PSEL Pin Sets Input Current Limit
          2. 8.2.3.3.2 Force Input Current Limit Detection
        4. 8.2.3.4 Input Voltage Limit Threshold Setting (VINDPM Threshold)
        5. 8.2.3.5 Converter Power-Up
      4. 8.2.4  Power Path Management
        1. 8.2.4.1 Dynamic Power Management
      5. 8.2.5  Battery Charging Management
        1. 8.2.5.1 Autonomous Charging Cycle
        2. 8.2.5.2 Battery Charging Profile
        3. 8.2.5.3 Charging Termination
        4. 8.2.5.4 Charging Safety Timer
      6. 8.2.6  Battery Monitor
      7. 8.2.7  Status Outputs (PG, STAT, and INT)
        1. 8.2.7.1 Power Good Indicator (PG)
        2. 8.2.7.2 Charging Status Indicator (STAT)
        3. 8.2.7.3 Interrupt to Host (INT)
      8. 8.2.8  Thermal Regulation and Thermal Shutdown
        1. 8.2.8.1 Thermal Protection in Buck Mode
      9. 8.2.9  Voltage and Current Monitoring in Buck
        1. 8.2.9.1 Voltage and Current Monitoring in Buck Mode
          1. 8.2.9.1.1 Input Overvoltage (ACOV)
          2. 8.2.9.1.2 System Overvoltage Protection (SYSOVP)
      10. 8.2.10 Battery Protection
        1. 8.2.10.1 Battery Overvoltage Protection (BATOVP)
        2. 8.2.10.2 Battery Over-Discharge Protection
      11. 8.2.11 Serial Interface
        1. 8.2.11.1 Data Validity
        2. 8.2.11.2 START and STOP Conditions
        3. 8.2.11.3 Byte Format
        4. 8.2.11.4 Acknowledge (ACK) and Not Acknowledge (NACK)
        5. 8.2.11.5 Slave Address and Data Direction Bit
        6. 8.2.11.6 Single Read and Write
        7. 8.2.11.7 Multi-Read and Multi-Write
    3. 8.3 Device Functional Modes
      1. 8.3.1 Host Mode and Default Mode
    4. 8.4 Register Map
      1. 8.4.1  REG00
      2. 8.4.2  REG01
      3. 8.4.3  REG02
      4. 8.4.4  REG03
      5. 8.4.5  REG04
      6. 8.4.6  REG05
      7. 8.4.7  REG06
      8. 8.4.8  REG07
      9. 8.4.9  REG08
      10. 8.4.10 REG09
      11. 8.4.11 REG0A
      12. 8.4.12 REG0B
      13. 8.4.13 REG0C
      14. 8.4.14 REG0D
      15. 8.4.15 REG0E
      16. 8.4.16 REG0F
      17. 8.4.17 REG11
      18. 8.4.18 REG12
      19. 8.4.19 REG13
      20. 8.4.20 REG14
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application Diagram
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Inductor Selection
        2. 9.2.2.2 Buck Input Capacitor
        3. 9.2.2.3 System Output Capacitor
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Detailed Description

The device is a highly integrated 3-A switch-mode battery charger for single cell Li-Ion and Li-polymer battery. It is highly integrated with the input reverse-blocking FET (RBFET, Q1), high-side switching FET (HSFET, Q2) , low-side switching FET (LSFET, Q3), and battery FET (BATFET, Q4). The device also integrates the boostrap diode for the high-side gate drive.

Functional Block Diagram

bq25898C fbd_slusch6.gif

Feature Description

Device Power-On-Reset (POR)

The internal bias circuits are powered from the higher voltage of VBUS and BAT. When VBUS rises above VVBUS_UVLOZ or BAT rises above VBAT_UVLOZ , the sleep comparator, battery depletion comparator and BATFET driver are active. I2C interface is ready for communication and all the registers are reset to default value. The host can access all the registers after POR.

Device Power Up from Battery without Input Source

If only battery is present and the voltage is above depletion threshold (VBAT_DPLZ), the BATFET turns on and connects battery to system. The REGN LDO stays off to minimize the quiescent current. The low RDS(ON) of BATFET and the low quiescent current on BAT minimize the conduction loss and maximize the battery run time. The device always monitors the discharge current through BATFET. When the system is overloaded or shorted (IBAT > IBATFET_OCP), the device turns off BATFET immediately until the input source plugs in again to re-enable BATFET.

Device Power Up from Input Source

When an input source is plugged in, the device checks the input source voltage to turn on REGN LDO and all the bias circuits. It detects and sets the input current limit before the buck converter is started when AUTO_DPDM_EN bit is set. The power up sequence from input source is as listed:

  1. Power Up REGN LDO
  2. Poor Source Qualification
  3. Input Source Type Detection based on PSEL to set default Input Current Limit (IINLIM) register and input source type
  4. Input Voltage Limit Threshold Setting (VINDPM threshold)
  5. Converter Power-up

Power Up REGN Regulation (LDO)

The REGN LDO supplies internal bias circuits as well as the HSFET and LSFET gate drive. The LDO also provides bias rail to TS external resistors. The pull-up rail of STAT can be connected to REGN as well. The REGN is enabled when all the below conditions are valid.

  1. VBUS above VVBUS_UVLOZ
  2. VBUS above VBAT + VSLEEPZ in buck mode
  3. After 220 ms delay is completed

If one of the above conditions is not valid, the device is in high impedance mode (HIZ) with REGN LDO off. The device draws less than IVBUS_HIZ from VBUS during HIZ state. The battery powers up the system when the device is in HIZ.

Poor Source Qualification

After REGN LDO powers up, the device checks the current capability of the input source. The input source has to meet the following requirements in order to start the buck converter.

  1. VBUS voltage below VACOV
  2. VBUS voltage above VVBUSMIN when pulling IBADSRC (typical 30mA)

Once the input source passes all the conditions above, the status register bit VBUS_GD is set high and the INT pin is pulsed to signal to the host. If the device fails the poor source detection, it repeats poor source qualification every 2 seconds.

Input Source Type Detection

After the VBUS_GD bit is set and REGN LDO is powered, the charger device runs Input Source Type Detection when AUTO_DPDM_EN bit is set.

After input source type detection, an INT pulse is asserted to the host. In addition, the following registers and pin are changed:

  1. Input Current Limit (IINLIM) register is changed to set current limit
  2. PG_STAT bit is set

The host can over-write IINLIM register to change the input current limit if needed. The charger input current is always limited by the lower of IINLIM register at all-time.

When AUTO_DPDM_EN is disabled, the Input Source Type Detection is bypassed. The Input Current Limit (IINLIM) register, VBUS_STAT, and SPD_STAT bits are unchanged from previous values.

PSEL Pin Sets Input Current Limit

The bq25898C has PSEL interface for input current limit setting to interface with USB PHY. It directly takes the USB PHY device output to decide whether the input is USB host or charging port. To implement USB100 in the system, the host can enter HiZ mode by setting EN_HIZ bit after 2 min charging with 500 mA input current limit.

Table 1. bq25898C Result

INPUT DETECTION BAT VOLTAGE PSEL PIN INPUT CURRENT LIMIT (IINLIM) SDP_STAT VBUS_STAT
USB SDP (USB500) X High 500 mA 1 001
Adapter X Low 1.5 A 010

Force Input Current Limit Detection

In host mode, the host can force the device to run by setting FORCE_DPDM bit. After the detection is completed, FORCE_DPDM bit returns to 0 by itself and Input Result is updated.

Input Voltage Limit Threshold Setting (VINDPM Threshold)

The device supports wide range of input voltage limit (3.9 V – 14 V) for high voltage charging and provides two methods to set Input Voltage Limit (VINDPM) threshold to facilitate autonomous detection.

  1. Absolute VINDPM (FORCE_VINDPM=1)
  2. By setting FORCE_VINDPM bit to 1, the VINDPM threshold setting algorithm is disabled. Register VINDPM is writable and allows host to set the absolute threshold of VINDPM function.

  3. Relative VINDPM based on VINDPM_OS registers (FORCE_VINDPM=0) (Default)

When FORCE_VINDPM bit is 0 (default), the VINDPM threshold setting algorithm is enabled. The VINDPM register is read only and the charger controls the register by using VINDPM Threshold setting algorithm. The algorithm allows a wide range of adapter (VVBUS_OP) to be used with flexible VINDPM threshold.

After Input Voltage Limit Threshold is set, an INT pulse is generated to signal to the host.

Converter Power-Up

After the input current limit is set, the converter is enabled and the HSFET and LSFET start switching. If battery charging is disabled, BATFET turns off. Otherwise, BATFET stays on to charge the battery.

The device provides soft-start when system rail is ramped up. When the system rail is below 2.2 V, the input current limit is forced to the lower of 200 mA or IINLIM register setting. After the system rises above 2.2 V, the device limits input current to the IILIM register.

As a battery charger, the device deploys a highly efficient 1.5 MHz step-down switching regulator. The fixed frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage, battery voltage, charge current and temperature, simplifying output filter design.

A type III compensation network allows using ceramic capacitors at the output of the converter. An internal saw-tooth ramp is compared to the internal error control signal to vary the duty cycle of the converter. The ramp height is proportional to the PMID voltage to cancel out any loop gain variation due to a change in input voltage.

In order to improve light-load efficiency, the device switches to PFM control at light load when battery is below minimum system voltage setting or charging is disabled. During the PFM operation, the switching duty cycle is set by the ratio of SYS and VBUS.

Power Path Management

The device accommodates a wide range of input sources from USB, wall adapter, to car battery. The device provides automatic power path selection to supply the system (SYS) from input source (VBUS), battery (BAT), or both.

Dynamic Power Management

To meet maximum current limit in USB spec and avoid over loading the adapter, the device features Dynamic Power Management (DPM), which continuously monitors the input current and input voltage. When input source is over-loaded, either the current exceeds the input current limit (IINLIM or IDPM_LIM) or the voltage falls below the input voltage limit (VINDPM). The device then reduces the charge current until the input current falls below the input current limit and the input voltage rises above the input voltage limit.

When the charge current is reduced to zero, but the input source is still overloaded, the system voltage starts to drop. Once the system voltage falls below the battery voltage, the device automatically enters the where the BATFET turns on and battery starts discharging so that the system is supported from both the input source and battery.

During DPM mode, the status register bits VDPM_STAT (VINDPM) and/or IDPM_STAT (IINDPM) is/are set high. Figure 9 shows the DPM response with 9V/1.2A adapter, 3.2-V battery, 2.8-A charge current and 3.4-V minimum system voltage setting.

bq25898C DPM_responce_slusbu7.gif Figure 9. DPM Response

Battery Charging Management

The device charges 1-cell Li-Ion battery with up to 3-A charge current for high capacity battery. The 5-mΩ BATFET improves charging efficiency and minimize the voltage drop during discharging.

Autonomous Charging Cycle

With battery charging enabled (CHG_CONFIG bit = 1, CE pin is low, and REG04[6:0] is not set to 0 mA), the device autonomously completes a charging cycle without host involvement. The device default charging parameters are listed in . The host can always control the charging operations and optimize the charging parameters by writing to the corresponding registers through I2C.

Table 2. Charging Parameter Default Setting

DEFAULT MODE bq25898C
Charging Voltage 4.208 V
Charging Current 0 A (charge disable)
Pre-charge Current 0 mA (precharge disabled)
Termination Current 256 mA
Safety Timer 12 hour

A new charge cycle starts when the following conditions are valid:

  • Converter starts
  • Battery charging is enabled by setting CHG_CONFIG bit, /CE pin is low and ICHG register is not 0 mA
  • No safety timer fault
  • BATFET is not forced to turn off (BATFET_DIS bit = 0)

The charger device automatically terminates the charging cycle when the charging current is below termination threshold, charge voltage is above recharge threshold, and device not in DPM mode or thermal regulation. When a full battery voltage is discharged below recharge threshold (threshold selectable via VRECHG bit), the device automatically starts a new charging cycle. After the charge is done, either toggle CE pin or CHG_CONFIG bit can initiate a new charging cycle.

The STAT output indicates the charging status of charging (LOW), charging complete or charge disable (HIGH) or charging fault (Blinking). The STAT output can be disabled by setting STAT_DIS bit. In addition, the status register (CHRG_STAT) indicates the different charging phases: 00-charging disable, 01-precharge, 10-fast charge (constant current) and constant voltage mode, 11-charging done. Once a charging cycle is completed, an INT is asserted to notify the host.

Battery Charging Profile

The device charges the battery in three phases: preconditioning, constant current and constant voltage. At the beginning of a charging cycle, the device checks the battery voltage and regulates current / voltage.

Table 3. Charging Current Setting

VBAT CHARGING CURRENT REG DEFAULT SETTING CHRG_STAT
< 2 V IBATSHORT 01
2 V – 3 V IPRECHG 0 mA (precharge disabled) 01
> 3 V ICHG 0 (charge disabled) 00

If the charger device is in DPM regulation or thermal regulation during charging, the charging current can be less than the programmed value. In this case, termination is temporarily disabled and the charging safety timer is counted at half the clock rate.

bq25898C Battery_Charging_Profile_slusce5.gif Figure 10. Battery Charging Profile

Charging Termination

The device terminates a charge cycle when the battery voltage is above recharge threshold, and the current is below termination current. After the charging cycle is completed, the BATFET turns off. The converter keeps running to power the system, and BATFET can turn on again to engage .

When termination occurs, the status register CHRG_STAT is set to 11, and an INT pulse is asserted to the host. Termination is temporarily disabled when the charger device is in input current, voltage or thermal regulation. Termination can be disabled by writing 0 to EN_TERM bit prior to charge termination.

Charging Safety Timer

The device has built-in safety timer to prevent extended charging cycle due to abnormal battery conditions. The safety timer is 4 hours when the battery is below VBATLOWV threshold. The user can program fast charge safety timer through I2C (CHG_TIMER bits). When safety timer expires, the fault register CHRG_FAULT bits are set to 11 and an INT is asserted to the host. The safety timer feature can be disabled via I2C by setting EN_TIMER bit.

During input voltage, current or thermal regulation, the safety timer counts at half clock rate as the actual charge current is likely to be below the register setting. For example, if the charger is in input current regulation (IDPM_STAT = 1) throughout the whole charging cycle, and the safety time is set to 5 hours, the safety timer will expire in 10 hours. This half clock rate feature can be disabled by writing 0 to TMR2X_EN bit.

Battery Monitor

The device includes a battery monitor to provide measurements of VBUS voltage, battery voltage, system voltage, thermistor ratio, and charging current, and charging current based on the device’s modes of operation. The measurements are reported in Battery Monitor Registers (REG0E-REG12). The battery monitor can be configured as two conversion modes by using CONV_RATE bit: one-shot conversion (default) and 1 second continuous conversion.

For one-shot conversion (CONV_RATE = 0), the CONV_START bit can be set to start the conversion. During the conversion, the CONV_START is set and it is cleared by the device when conversion is completed. The conversion result is ready after tCONV (maximum 1 second).

For continuous conversion (CONV_RATE = 1), the CONV_RATE bit can be set to initiate the conversion. During active conversion, the CONV_START is set to indicate conversion is in progress. The battery monitor provides conversion result every 1 second automatically. The battery monitor exits continuous conversion mode when CONV_RATE is cleared.

When battery monitor is active, the REGN power is enabled and can increase device quiescent current.

Table 4. Battery Monitor Modes of Operation

PARAMETER REGISTER MODES OF OPERATION
CHARGE MODE DISABLE CHARGE MODE BATTERY ONLY MODE
Battery Voltage (VBAT) REG0E Yes Yes Yes
System Voltage (VSYS) REG0F Yes Yes Yes
VBUS Voltage (VVBUS) REG11 Yes Yes NA
Charge Current (IBAT) REG12 Yes NA NA

Status Outputs (PG, STAT, and INT)

Power Good Indicator (PG)

In bq25898C, the PG goes LOW to indicate a good input source when:

  1. VBUS above VVBUS_UVLO
  2. VBUS above battery (not in sleep)
  3. VBUS below VACOV threshold
  4. VBUS above VVBUSMIN (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
  5. Completed Input Source Type Detection

Charging Status Indicator (STAT)

The device indicates charging state on the open drain STAT pin. The STAT pin can drive LED as shown in . The STAT pin function can be disable by setting STAT_DIS bit.

Table 5. STAT Pin State

CHARGING STATE STAT INDICATOR
Charging in progress (including recharge) LOW
Charging complete HIGH
Sleep mode, charge disable HIGH
Charge suspend (Input overvoltage, timer fault, input or system overvoltage) blinking at 1 Hz

Interrupt to Host (INT)

In some applications, the host does not always monitor the charger operation. The INT notifies the system on the device operation. The following events will generate 256-µs INT pulse.

  • USB/adapter source identified (through PSEL detection)
  • Good input source detected
    • VBUS above battery (not in sleep)
    • VBUS below VACOV threshold
    • VBUS above VVBUSMIN (typical 3.8 V) when IBADSRC (typical 30 mA) current is applied (not a poor source)
  • Input removed
  • Charge Complete
  • Any FAULT event in REG0C

When a fault occurs, the charger device sends out INT and keeps the fault state in REG0C until the host reads the fault register. Before the host reads REG0C and all the faults are cleared, the charger device would not send any INT upon new faults. To read the current fault status, the host has to read REG0C two times consecutively. The 1st read reports the pre-existing fault register status and the 2nd read reports the current fault register status.

Thermal Regulation and Thermal Shutdown

Thermal Protection in Buck Mode

The device monitors the internal junction temperature TJ to avoid overheat the chip and limits the IC surface temperature in buck mode. When the internal junction temperature exceeds the preset thermal regulation limit (TREG bits), the device lowers down the charge current. The wide thermal regulation range from 60ºC to 120ºC allows the user to optimize the system thermal performance.

During thermal regulation, the actual charging current is usually below the programmed battery charging current. Therefore, termination is disabled, the safety timer runs at half the clock rate, and the status register THERM_STAT bit goes high.

Additionally, the device has thermal shutdown to turn off the converter and BATFET when IC surface temperature exceeds TSHUT. The fault register CHRG_FAULT is set to 10 and an INT is asserted to the host. The BATFET and converter is enabled to recover when IC temperature is below TSHUT_HYS.

Voltage and Current Monitoring in Buck

Voltage and Current Monitoring in Buck Mode

The device closely monitors the input and system voltage, as well as HSFET current for safe buck mode operations.

Input Overvoltage (ACOV)

The input voltage for buck mode operation is VVBUS_OP. If VBUS voltage exceeds VACOV, the device stops switching immediately. During input over voltage (ACOV), the fault register CHRG_FAULT bits sets to 01. An INT is asserted to the host.

System Overvoltage Protection (SYSOVP)

The charger device clamps the system voltage during load transient so that the components connect to system would not be damaged due to high voltage. When SYSOVP is detected, the converter stops immediately to clamp the overshoot.

Battery Protection

Battery Overvoltage Protection (BATOVP)

The battery overvoltage limit is clamped at 4% above the battery regulation voltage. When battery over voltage occurs, the charger device immediately disables charge. The fault register BAT_FAULT bit goes high and an INT is asserted to the host.

Battery Over-Discharge Protection

When battery is discharged below VBAT_DPL, the BATFET is turned off to protect battery from over discharge. To recover from over-discharge, an input source is required at VBUS. When an input source is plugged in, the BATFET turns on. Thy is charged with IBATSHORT (typically 100 mA) current when the VBAT < VSHORT, or precharge current as set in IPRECHG register when the battery voltage is between VSHORT and VBATLOWV.

Serial Interface

The device uses I2C compatible interface for flexible charging parameter programming and instantaneous device status reporting. I2C is a bi-directional 2-wire serial interface. Only two open-drain bus lines are required: a serial data line (SDA) and a serial clock line (SCL). Devices can be considered as masters or slaves when performing data transfers. A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer. At that time, any device addressed is considered a slave.

The device operates as a slave device with address 6BH, receiving control inputs from the master device like micro controller or a digital signal processor through REG00-REG14. Register read beyond REG14 (0x14) returns 0xFF. The I2C interface supports both standard mode (up to 100 kbits), and fast mode (up to 400 kbits). When the bus is free, both lines are HIGH. The SDA and SCL pins are open drain and must be connected to the positive supply voltage via a current source or pull-up resistor.

Data Validity

The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. One clock pulse is generated for each data bit transferred.

bq25898C Bit_Transfer_on_the_I2C_Bus_SLUSAW5.gif Figure 11. Bit Transfer on the I2C Bus

START and STOP Conditions

All transactions begin with a START (S) and can be terminated by a STOP (P). A HIGH to LOW transition on the SDA line while SCl is HIGH defines a START condition. A LOW to HIGH transition on the SDA line when the SCL is HIGH defines a STOP condition.

START and STOP conditions are always generated by the master. The bus is considered busy after the START condition, and free after the STOP condition.

bq25898C START_STOP_conditions_slusbu7.gif Figure 12. START and STOP conditions

Byte Format

Every byte on the SDA line must be 8 bits long. The number of bytes to be transmitted per transfer is unrestricted. Each byte has to be followed by an Acknowledge bit. Data is transferred with the Most Significant Bit (MSB) first. If a slave cannot receive or transmit another complete byte of data until it has performed some other function, it can hold the clock line SCL low to force the master into a wait state (clock stretching). Data transfer then continues when the slave is ready for another byte of data and release the clock line SCL.

bq25898C Data_tranfer_I2C_Bus_slusbu7.gif Figure 13. Data Transfer on the I2C Bus

Acknowledge (ACK) and Not Acknowledge (NACK)

The acknowledge takes place after every byte. The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent. All clock pulses, including the acknowledge 9th clock pulse, are generated by the master.

The transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse.

When SDA remains HIGH during the 9th clock pulse, this is the Not Acknowledge signal. The master can then generate either a STOP to abort the transfer or a repeated START to start a new transfer.

Slave Address and Data Direction Bit

After the START, a slave address is sent. This address is 7 bits long followed by the eighth bit as a data direction bit (bit R/W). A zero indicates a transmission (WRITE) and a one indicates a request for data (READ).

bq25898C Complete_data_tranfer_slusbu7.gif Figure 14. Complete Data Transfer

Single Read and Write

bq25898C Single_Write_SLUSAW5.gif Figure 15. Single Write
bq25898C Single_Read_SLUSAW5.gif Figure 16. Single Read

If the register address is not defined, the charger IC send back NACK and go back to the idle state.

Multi-Read and Multi-Write

The charger device supports multi-read and multi-write on REG00 through REG14 except REG0C.

bq25898C Multi_write_slusbu7.gif Figure 17. Multi-Write
bq25898C Multi_read_slusbu7.gif Figure 18. Multi-Read

REG0C is a fault register. It keeps all the fault information from last read until the host issues a new read. For example, if Charge Safety Timer Expiration fault occurs but recovers later, the fault register REG0C reports the fault when it is read the first time, but returns to normal when it is read the second time. In order to get the fault information at present, the host has to read REG0C for the second time. The only exception is NTC_FAULT which always reports the actual condition on the TS pin. In addition, REG0C does not support multi-read and multi-write.

Device Functional Modes

Host Mode and Default Mode

The device is a host controlled charger. The device cannot operate in default mode without host management because default charge current is set to 0 mA (charge disabled).

All the device parameters can be programmed by the host. To keep the device in host mode, the host has to reset the watchdog timer by writing 1 to WD_RST bit before the watchdog timer expires (WATCHDOG_FAULT bit is set), or disable watchdog timer by setting WATCHDOG bits=00.

When the watchdog timer (WATCHDOG_FAULT bit = 1) is expired, the device returns to default mode and all registers are reset to default values except IINLIM, VINDPM, VINDPM_OS bits.

bq25898C Wathdog_timer_flowchart_slusbu7.gif Figure 19. Watchdog Timer Flow Chart

Register Map

I2C Slave Address: 6BH (1101011B + R/W)

REG00

Figure 20. REG00
7 6 5 4 3 2 1 0
0 1 0 1 1 1 0 0
R/W R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6. REG00

Bit Field Type Reset Description
7 EN_HIZ R/W by REG_RST
by Watchdog
Enable HIZ Mode
0 – Disable (default)
1 – Enable
6 Reserved R N/A Reserved Always reads 1
5 IINLIM[5] R/W by REG_RST 1600mA Input Current Limit
Offset: 100mA
Range: 100mA (000000) – 3.25A (111111)
Default:011100 (1500mA)
(Actual input current limit is the lower of I2C or ILIM pin)
IINLIM bits are changed automatically after input source type detection is completed
4 IINLIM[4] R/W by REG_RST 800mA
3 IINLIM[3] R/W by REG_RST 400mA
2 IINLIM[2] R/W by REG_RST 200mA
1 IINLIM[1] R/W by REG_RST 100mA
0 IINLIM[0] R/W by REG_RST 50mA

REG01

Figure 21. REG01
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
R R R R R R R R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 7. REG01

Bit Field Type Reset Description
7 Reserved R N/A Reserved, Always read 0
6 Reserved R N/A Reserved, Always read 0
5 Reserved R N/A Reserved, Always read 0
4 Reserved R N/A Reserved, Always read 0
3 Reserved R N/A Reserved, Always read 0
2 Reserved R N/A Reserved, Always read 0
1 Reserved R N/A Reserved, Always read 0
0 VDPM_OS R/W by REG_RST VINDPM offset threshold
Default 600mV (1)
0 - 400mA offset
1 - 600mA offset

REG02

Figure 22. REG02
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1
R/W R/W R R R R R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 8. REG02

Bit Field Type Reset Description
7 CONV_START R/W by REG_RST
by Watchdog
ADC Conversion Start Control
0 – ADC conversion not active (default).
1 – Start ADC Conversion
This bit is read-only when CONV_RATE = 1. The bit stays high during ADC conversion and during input source detection.
6 CONV_RATE R/W by REG_RST
by Watchdog
ADC Conversion Rate Selection
0 – One shot ADC conversion (default)
1 – Start 1s Continuous Conversion
5 Reserved R N/A Reserved, Always read 0
4 Reserved R N/A Reserved, Always read 0
3 Reserved R N/A Reserved, Always read 0
2 Reserved R N/A Reserved, Always read 0
1 FORCE_DPDM R/W by REG_RST
by Watchdog
Force PSEL Detection
0 – Not in PSEL detection (default)
1 – Force PSEL detection
0 AUTO_DPDM_EN R/W by REG_RST Automatic Detection Enable
0 –Disable PSEL detection when VBUS is plugged-in
1 –Enable PEL detection when VBUS is plugged-in (default)

REG03

Figure 23. REG03
7 6 5 4 3 2 1 0
0 0 0 1 1 0 1 0
R R/W R R/W R/W R/W R/W R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 9. REG03

Bit Field Type Reset Description
7 Reserved R N/A Reserved Always read 0
6 WD_RST R/W by REG_RST
by Watchdog
I2C Watchdog Timer Reset
0 – Normal (default)
1 – Reset (Back to 0 after timer reset)
5 Reserved R N/A Reserved Always read 0
4 CHG_CONFIG R/W by REG_RST
by Watchdog
Charge Enable Configuration
0 - Charge Disable
1- Charge Enable (default)
3 SYS_MIN[2] R/W by REG_RST 0.4V Minimum System Voltage Limit
Offset: 3.0V
Range 3.0V-3.7V
Default: 3.5V (101)
2 SYS_MIN[1] R/W by REG_RST 0.2V
1 SYS_MIN[0] R/W by REG_RST 0.1V
0 Reserved R N/A Reserved Always read 0

REG04

Figure 24. REG04
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
R R R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 10. REG04

Bit Field Type Reset Description
7 Reserved R N/A Reserved Always reads 0
6 Reserved R N/A Reserved Always reads 0
5 ICHG[5] R/W by REG_RST
by Watchdog
2048mA Fast Charge Current Limit
Offset: 0mA
Range: 0mA (000000) – 3008mA (101111) Default: 0mA (000000)
Note:
ICHG=000000 (0mA) disables both fast charge and precharge
ICHG > 101111 (3008mA) is clamped to register value 101111 (3008mA)
4 ICHG[4] R/W by REG_RST
by Watchdog
1024mA
3 ICHG[3] R/W by REG_RST
by Watchdog
512mA
2 ICHG[2] R/W by REG_RST
by Watchdog
256mA
1 ICHG[1] R/W by REG_RST
by Watchdog
128mA
0 ICHG[0] R/W by REG_RST
by Watchdog
64mA

REG05

Figure 25. REG05
7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 1
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 11. REG05

Bit Field Type Reset Description
7 IPRECHG[3] R/W by REG_RST
by Watchdog
512mA Precharge Current Limit
Offset: 64mA
Range: 64mA – 1024mA
Default: 0mA when REG04[5:0] = 000000
6 IPRECHG[2] R/W by REG_RST
by Watchdog
256mA
5 IPRECHG[1] R/W by REG_RST
by Watchdog
128mA
4 IPRECHG[0] R/W by REG_RST
by Watchdog
64mA
3 ITERM[3] R/W by REG_RST
by Watchdog
512mA Termination Current Limit
Offset: 64mA
Range: 64mA – 1024mA
Default: 256mA (0011)
2 ITERM[2] R/W by REG_RST
by Watchdog
256mA
1 ITERM[1] R/W by REG_RST
by Watchdog
128mA
0 ITERM[0] R/W by REG_RST
by Watchdog
64mA

REG06

Figure 26. REG06
7 6 5 4 3 2 1 0
0 1 0 1 1 1 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 12. REG06

Bit Field Type Reset Description
7 VREG[5] R/W by REG_RST
by Watchdog
512mV Charge Voltage Limit
Offset: 3.840V
Range: 3.840V – 4.608V (110000)
Default: 4.208V (010111)
Note:
VREG > 110000 (4.608V) is clamped to register value 110000 (4.608V)
6 VREG[4] R/W by REG_RST
by Watchdog
256mV
5 VREG[3] R/W by REG_RST
by Watchdog
128mV
4 VREG[2] R/W by REG_RST
by Watchdog
64mV
3 VREG[1] R/W by REG_RST
by Watchdog
32mV
2 VREG[0] R/W by REG_RST
by Watchdog
16mV
1 BATLOWV R/W by REG_RST
by Watchdog
Battery Precharge to Fast Charge Threshold
0 – 2.8V
1 – 3.0V (default)
0 VRECHG R/W by REG_RST
by Watchdog
Battery Recharge Threshold Offset
(below Charge Voltage Limit)
0 – 100mV (VRECHG) below VREG (REG06[7:2]) (default)
1 – 200mV (VRECHG) below VREG (REG06[7:2])

REG07

Figure 27. REG07
7 6 5 4 3 2 1 0
1 0 0 1 1 1 0 1
R/W R/W R/W R/W R/W R/W R/W R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 13. REG07

Bit Field Type Reset Description
7 EN_TERM R/W by REG_RST
by Watchdog
Charging Termination Enable
0 – Disable
1 – Enable (default)
6 STAT_DIS R/W by REG_RST
by Watchdog
STAT Pin Disable
0 – Enable STAT pin function (default)
1 – Disable STAT pin function
5 WATCHDOG[1] R/W by REG_RST
by Watchdog
I2C Watchdog Timer Setting
00 – Disable watchdog timer
01 – 40s (default)
10 – 80s
11 – 160s
4 WATCHDOG[0] R/W by REG_RST
by Watchdog
3 EN_TIMER R/W by REG_RST
by Watchdog
Charging Safety Timer Enable
0 – Disable
1 – Enable (default)
2 CHG_TIMER[1] R/W by REG_RST
by Watchdog
Fast Charge Timer Setting
00 – 5 hrs
01 – 8 hrs
10 – 12 hrs (default)
11 – 20 hrs
1 CHG_TIMER[0] R/W by REG_RST
by Watchdog
0 Reserved R N/A Reserved always reads 1

REG08

Figure 28. REG08
7 6 5 4 3 2 1 0
0 0 0 0 0 0 1 1
R R R R R R R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. REG08

Bit Field Type Reset Description
7 Reserved R N/A Reserved Always reads 000
6 Reserved R N/A
5 Reserved R N/A
4 Reserved R N/A Reserved Always reads 000
3 Reserved R N/A
2 Reserved R N/A
1 TREG[1] R/W by REG_RST
by Watchdog
Thermal Regulation Threshold
00 – 60°C
01 – 80°C
10 – 100°C
11 – 120°C (default)
0 TREG[0] R/W by REG_RST
by Watchdog

REG09

Figure 29. REG09
7 6 5 4 3 2 1 0
0 1 0 0 0 1 0 0
R R/W R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 15. REG09

Bit Field Type Reset Description
7 Reserved R N/A Reserved Always reads 0
6 TMR2X_EN R/W by Watchdog Safety Timer Setting during DPM or Thermal Regulation
0 – Safety timer not slowed by 2X during input DPM or thermal regulation
1 – Safety timer slowed by 2X during input DPM or thermal regulation (default)
5 BATFET_DIS R/W by REG_RST Force BATFET off to enable ship mode with tSM_DLY delay time
0 – Allow BATFET turn on (default)
1 – Force BATFET off
4 Reserved R N/A Reserved Always reads 0
3 Reserved R N/A Reserved Always reads 0
2 Reserved R N/A Reserved Always reads 1
1 Reserved R N/A Reserved Always reads 0
0 Reserved R N/A Reserved Always reads 0

REG0A

Figure 30. REG0A
7 6 5 4 3 2 1 0
0 1 1 1 0 1 0 0
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 16. REG0A

Bit Field Type Reset Description
7 Reserved R N/A Reserved Always reads 0
6 Reserved R N/A Reserved Always reads 1
5 Reserved R N/A Reserved Always reads 1
4 Reserved R N/A Reserved Always reads 1
3 Reserved R N/A Reserved Always reads 0
2 Reserved R N/A Reserved Always reads 1
1 Reserved R N/A Reserved Always reads 0
0 Reserved R N/A Reserved Always reads 0

REG0B

Figure 31. REG0B
7 6 5 4 3 2 1 0
x x x x x x 1 x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17. REG0B

Bit Field Type Reset Description
7 VBUS_STAT[2] R N/A VBUS Status register
000: No Input
001: USB Host SDP
010: Adapter (3.25A)
111: N/A
Note: Software current limit is reported in IINLIM register
6 VBUS_STAT[1] R N/A
5 VBUS_STAT[0] R N/A
4 CHRG_STAT[1] R N/A Charging Status
00 – Not Charging
01 – Pre-charge ( < VBATLOWV)
10 – Fast Charging
11 – Charge Termination Done
3 CHRG_STAT[0] R N/A
2 PG_STAT R N/A Power Good Status
0 – Not Power Good
1 – Power Good
1 Reserved R N/A Reserved
0 VSYS_STAT R N/A VSYS Regulation Status
0 – Not in VSYSMIN regulation (BAT > VSYSMIN)
1 – In VSYSMIN regulation (BAT < VSYSMIN)

REG0C

Figure 32. REG0C
7 6 5 4 3 2 1 0
x x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 18. REG0C

Bit Field Type Reset Description
7 WATCHDOG_FAULT R N/A Watchdog Fault Status
Status 0 – Normal
1- Watchdog timer expiration
6 Reserved R N/A Reserved
5 CHRG_FAULT[1] R N/A Charge Fault Status
00 – Normal
01 – Input fault (VBUS > VACOV or VBAT < VBUS < VVBUSMIN(typical 3.8V) )
10 - Thermal shutdown
11 – Charge Safety Timer Expiration
4 CHRG_FAULT[0] R N/A
3 BAT_FAULT R N/A Battery Fault Status
0 – Normal
1 – BATOVP (VBAT > VBATOVP)
2 Reserved R N/A Reserved
1 Reserved R N/A Reserved
0 Reserved R N/A Reserved

REG0D

Figure 33. REG0D
7 6 5 4 3 2 1 0
0 0 0 1 0 0 1 0
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 19. REG0D

Bit Field Type Reset Description
7 FORCE_VINDPM R/W by REG_RST VINDPM Threshold Setting Method
0 – Run Relative VINDPM Threshold (default)
1 – Run Absolute VINDPM Threshold
6 VINDPM[6] R/W by REG_RST 6400mV Absolute VINDPM Threshold
Offset: 2.6V
Range: 3.9V (0001101) – 15.3V (1111111)
Default: 4.4V (0010010)
Note:
Value < 0001101 is clamped to 3.9V (0001101)
Register is read only when FORCE_VINDPM=0 and can be written by internal control based on relative VINDPM threshold setting
Register can be read/write when FORCE_VINDPM = 1
5 VINDPM[5] R/W by REG_RST 3200mV
4 VINDPM[4] R/W by REG_RST 1600mV
3 VINDPM[3] R/W by REG_RST 800mV
2 VINDPM[2] R/W by REG_RST 400mV
1 VINDPM[1] R/W by REG_RST 200mV
0 VINDPM[0] R/W by REG_RST 100mV

REG0E

Figure 34. REG0E
7 6 5 4 3 2 1 0
x x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 20. REG0E

Bit Field Type Reset Description
7 THERM_STAT R N/A Thermal Regulation Status
0 – Normal
1 – In Thermal Regulation
6 BATV[6] R N/A 1280mV ADC conversion of Battery Voltage (VBAT)
5 BATV[5] R N/A 640mV
4 BATV[4] R N/A 320mV
3 BATV[3] R N/A 160mV
2 BATV[2] R N/A 80mV
1 BATV[1] R N/A 40mV
0 BATV[0] R N/A 20mV

REG0F

Figure 35. REG0F
7 6 5 4 3 2 1 0
0 x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 21. REG0F

Bit Field Type Reset Description
7 Reserved R N/A Reserved: Always reads 0
6 SYSV[6] R N/A 1280mV ADC conversion of System Voltage (VSYS)
5 SYSV[5] R N/A 640mV
4 SYSV[4] R N/A 320mV
3 SYSV[3] R N/A 160mV
2 SYSV[2] R N/A 80mV
1 SYSV[1] R N/A 40mV
0 SYSV[0] R N/A 20mV

REG11

Figure 36. REG11
7 6 5 4 3 2 1 0
x x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 22. REG11

Bit Field Type Reset Description
7 VBUS_GD R N/A VBUS Good Status
0 – Not VBUS attached
1 – VBUS Attached
6 VBUSV[6] R N/A 6400mV ADC conversion of VBUS voltage (VBUS)
Offset: 2.6V
Range 2.6V (0000000) – 15.3V (1111111)
Default: 2.6V (0000000)
5 VBUSV[5] R N/A 3200mV
4 VBUSV[4] R N/A 1600mV
3 VBUSV[3] R N/A 800mV
2 VBUSV[2] R N/A 400mV
1 VBUSV[1] R N/A 200mV
0 VBUSV[0] R N/A 100mV

REG12

Figure 37. REG12
7 6 5 4 3 2 1 0
0 x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 23. REG12

Bit Field Type Reset Description
7 Reserved R N/A Always reads 0
6 ICHGR[6] R N/A 3200mA ADC conversion of Charge Current (IBAT) when VBAT > VBATSHORT
Offset: 0mA
Range 0mA (0000000) – 6350mA (1111111)
Default: 0mA (0000000)
Note:
This register returns 0000000 for VBAT < VBATSHORT
5 ICHGR[5] R N/A 1600mA
4 ICHGR[4] R N/A 800mA
3 ICHGR[3] R N/A 400mA
2 ICHGR[2] R N/A 200mA
1 ICHGR[1] R N/A 100mA
0 ICHGR[0] R N/A 50mA

REG13

Figure 38. REG13
7 6 5 4 3 2 1 0
x x x x x x x x
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 24. REG13

Bit Field Type Reset Description
7 VDPM_STAT R N/A VINDPM Status
0 – Not in VINDPM
1 – VINDPM
6 IDPM_STAT R N/A IINDPM Status
0 – Not in IINDPM
1 – IINDPM
5 IDPM_LIM[5] R N/A 1600mA Input Current Limit in effect
4 IDPM_LIM[4] R N/A 800mA
3 IDPM_LIM[3] R N/A 400mA
2 IDPM_LIM[2] R N/A 200mA
1 IDPM_LIM[1] R N/A 100mA
0 IDPM_LIM[0] R N/A 50mA

REG14

Figure 39. REG14
7 6 5 4 3 2 1 0
0 x 0 0 1 1 0 1
R/W R R R R R R R
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 25. REG14

Bit Field Type Reset Description
7 REG_RST R/W N/A Register Reset
0 – Keep current register setting (default)
1 – Reset to default register value and reset safety timer
Note:
Reset to 0 after register reset is completed
6 Reserved R N/A Reserved
5 PN[2] R N/A Device Configuration
001: bq25898C
4 PN[1] R N/A
3 PN[0] R N/A
2 Reserved R N/A Reserved Always reads 1
1 DEV_REV[1] R N/A Device Revision: 01
0 DEV_REV[0] R N/A