JAJSRJ8B September   2019  – October 2023 BQ75614-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 概要 (続き)
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Power Supplies
        1. 8.3.1.1 AVAO_REF and AVDD_REF
        2. 8.3.1.2 LDOIN
        3. 8.3.1.3 AVDD
        4. 8.3.1.4 DVDD
        5. 8.3.1.5 CVDD and NEG5V
        6. 8.3.1.6 TSREF
      2. 8.3.2 Measurement System
        1. 8.3.2.1 Main ADC
          1. 8.3.2.1.1 Cell Voltage Measurements
            1. 8.3.2.1.1.1 Analog Front End
            2. 8.3.2.1.1.2 VC Channel Measurements
            3. 8.3.2.1.1.3 Post-ADC Digital LPF
            4. 8.3.2.1.1.4 SRP and SRN Measurements
          2. 8.3.2.1.2 Temperature Measurements
            1. 8.3.2.1.2.1 DieTemp1 Measurement
            2. 8.3.2.1.2.2 GPIOs and TSREF Measurements
          3. 8.3.2.1.3 Main ADC Operation Control
            1. 8.3.2.1.3.1 Operation Modes and Status
        2. 8.3.2.2 AUX ADC
          1. 8.3.2.2.1 AUX Cell Voltage Measurements
            1. 8.3.2.2.1.1 AUX Analog Front End
            2. 8.3.2.2.1.2 CB and Current Sense Channel Measurements
          2. 8.3.2.2.2 AUX Temperature Measurements
            1. 8.3.2.2.2.1 DieTemp2 Measurement
            2. 8.3.2.2.2.2 AUX GPIO Measurements
          3. 8.3.2.2.3 MISC Measurements
          4. 8.3.2.2.4 AUX ADC Operation Control
        3. 8.3.2.3 Synchronization between MAIN and AUX ADC Measurements
        4. 8.3.2.4 CS ADC
      3. 8.3.3 Cell Balancing
        1. 8.3.3.1 Set Up Cell Balancing
          1. 8.3.3.1.1 Step 1: Determine Balancing Channels
          2. 8.3.3.1.2 Step 2: Select Balancing Control Methods
          3. 8.3.3.1.3 Step 3a: Balancing Thermal Management
          4. 8.3.3.1.4 Step 3b: Option to Stop On Cell Voltage Threshold
          5. 8.3.3.1.5 Step 3c: Option to Stop at Fault
        2. 8.3.3.2 Cell Balancing in SLEEP Mode
        3. 8.3.3.3 Pause and Stop Cell Balancing
          1. 8.3.3.3.1 Cell Balancing Pause
          2. 8.3.3.3.2 Cell Balancing Stop
          3. 8.3.3.3.3 Remaining CB Time
      4. 8.3.4 Integrated Hardware Protectors
        1. 8.3.4.1 OVUV Protectors
          1. 8.3.4.1.1 OVUV Operation Modes
          2. 8.3.4.1.2 OVUV Control and Status
            1. 8.3.4.1.2.1 OVUV Control
            2. 8.3.4.1.2.2 OVUV Status
        2. 8.3.4.2 OTUT Protector
          1. 8.3.4.2.1 OTUT Operation Modes
          2. 8.3.4.2.2 OTUT Control and Status
            1. 8.3.4.2.2.1 OTUT Control
            2. 8.3.4.2.2.2 OTUT Status
      5. 8.3.5 GPIO Configuration
      6. 8.3.6 Communication, OTP, Diagnostic Control
        1. 8.3.6.1 Communication
          1. 8.3.6.1.1 Serial Interface
            1. 8.3.6.1.1.1 UART Physical Layer
              1. 8.3.6.1.1.1.1 UART Transmitter
              2. 8.3.6.1.1.1.2 UART Receiver
              3. 8.3.6.1.1.1.3 COMM CLEAR
            2. 8.3.6.1.1.2 Command and Response Protocol
              1. 8.3.6.1.1.2.1 Transaction Frame Structure
                1. 8.3.6.1.1.2.1.1 Frame Initialization Byte
                2. 8.3.6.1.1.2.1.2 Device Address Byte
                3. 8.3.6.1.1.2.1.3 Register Address Bytes
                4. 8.3.6.1.1.2.1.4 Data Bytes
                5. 8.3.6.1.1.2.1.5 CRC Bytes
                6. 8.3.6.1.1.2.1.6 Calculating Frame CRC Value
                7. 8.3.6.1.1.2.1.7 Verifying Frame CRC
              2. 8.3.6.1.1.2.2 Transaction Frame Examples
                1. 8.3.6.1.1.2.2.1 Single Device Read/Write
          2. 8.3.6.1.2 Communication Timeout
            1. 8.3.6.1.2.1 Short Communication Timeout
            2. 8.3.6.1.2.2 Long Communication Timeout
          3. 8.3.6.1.3 SPI Master
          4. 8.3.6.1.4 SPI Loopback
        2. 8.3.6.2 Fault Handling
          1. 8.3.6.2.1 Fault Status Hierarchy
            1. 8.3.6.2.1.1 Debug Registers
          2. 8.3.6.2.2 Fault Masking and Reset
            1. 8.3.6.2.2.1 Fault Masking
            2. 8.3.6.2.2.2 Fault Reset
          3. 8.3.6.2.3 Fault Signaling
        3. 8.3.6.3 Nonvolatile Memory
          1. 8.3.6.3.1 OTP Page Status
          2. 8.3.6.3.2 OTP Programming
        4. 8.3.6.4 Diagnostic Control/Status
          1. 8.3.6.4.1 Power Supplies Check
            1. 8.3.6.4.1.1 Power Supply Diagnostic Check
            2. 8.3.6.4.1.2 Power Supply BIST
          2. 8.3.6.4.2 Thermal Shutdown and Warning Check
            1. 8.3.6.4.2.1 Thermal Shutdown
            2. 8.3.6.4.2.2 Thermal Warning
          3. 8.3.6.4.3 Oscillators Watchdog
          4. 8.3.6.4.4 OTP Error Check
            1. 8.3.6.4.4.1 OTP CRC Test and Faults
            2. 8.3.6.4.4.2 OTP Margin Read
            3. 8.3.6.4.4.3 Error Check and Correct (ECC) OTP
          5. 8.3.6.4.5 Integrated Hardware Protector Check
            1. 8.3.6.4.5.1 Parity Check
            2. 8.3.6.4.5.2 OVUV and OTUT DAC Check
            3. 8.3.6.4.5.3 OVUV Protector BIST
            4. 8.3.6.4.5.4 OTUT Protector BIST
          6. 8.3.6.4.6 Diagnostic Through ADC Comparison
            1. 8.3.6.4.6.1 Cell Voltage Measurement Check
            2. 8.3.6.4.6.2 Temperature Measurement Check
            3. 8.3.6.4.6.3 Cell Balancing FETs Check
            4. 8.3.6.4.6.4 VC and CB Open Wire Check
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power Modes
        1. 8.4.1.1 SHUTDOWN Mode
          1. 8.4.1.1.1 Exit SHUTDOWN Mode
          2. 8.4.1.1.2 Enter SHUTDOWN Mode
        2. 8.4.1.2 SLEEP Mode
          1. 8.4.1.2.1 Exit SLEEP Mode
          2. 8.4.1.2.2 Enter SLEEP Mode
        3. 8.4.1.3 ACTIVE Mode
          1. 8.4.1.3.1 Exit ACTIVE Mode
          2. 8.4.1.3.2 Enter ACTIVE Mode From SHUTDOWN Mode
          3. 8.4.1.3.3 Enter ACTIVE Mode From SLEEP Mode
      2. 8.4.2 Device Reset
      3. 8.4.3 Ping
        1. 8.4.3.1 Ping
    5. 8.5 Register Maps
      1. 8.5.1 OTP Shadow Register Summary
      2. 8.5.2 Read/Write Register Summary
      3. 8.5.3 Read-Only Register Summary
      4. 8.5.4 Register Field Descriptions
        1. 8.5.4.1  Device Addressing Setup
          1. 8.5.4.1.1 DIR0_ADDR_OTP
          2. 8.5.4.1.2 DIR1_ADDR_OTP
          3. 8.5.4.1.3 CUST_MISC1 through CUST_MISC8
          4. 8.5.4.1.4 DIR0_ADDR
          5. 8.5.4.1.5 DIR1_ADDR
        2. 8.5.4.2  Device ID and Scratch Pad
          1. 8.5.4.2.1 PARTID
          2. 8.5.4.2.2 DEV_REVID
          3. 8.5.4.2.3 DIE_ID1 through DIE_ID9
        3. 8.5.4.3  General Configuration and Control
          1. 8.5.4.3.1  DEV_CONF
          2. 8.5.4.3.2  ACTIVE_CELL
          3. 8.5.4.3.3  PWR_TRANSIT_CONF
          4. 8.5.4.3.4  COMM_TIMEOUT_CONF
          5. 8.5.4.3.5  TX_HOLD_OFF
          6. 8.5.4.3.6  COMM_CTRL
          7. 8.5.4.3.7  CONTROL1
          8. 8.5.4.3.8  CONTROL2
          9. 8.5.4.3.9  CUST_CRC_HI
          10. 8.5.4.3.10 CUST_CRC_LO
          11. 8.5.4.3.11 CUST_CRC_RSLT_HI
          12. 8.5.4.3.12 CUST_CRC_RSLT_LO
        4. 8.5.4.4  Operation Status
          1. 8.5.4.4.1 DIAG_STAT
          2. 8.5.4.4.2 ADC_STAT1
          3. 8.5.4.4.3 ADC_STAT2
          4. 8.5.4.4.4 GPIO_STAT
          5. 8.5.4.4.5 BAL_STAT
          6. 8.5.4.4.6 DEV_STAT
        5. 8.5.4.5  ADC Configuration and Control
          1. 8.5.4.5.1  ADC_CONF1
          2. 8.5.4.5.2  ADC_CONF2
          3. 8.5.4.5.3  MAIN_ADC_CAL1
          4. 8.5.4.5.4  MAIN_ADC_CAL2
          5. 8.5.4.5.5  AUX_ADC_CAL1
          6. 8.5.4.5.6  AUX_ADC_CAL2
          7. 8.5.4.5.7  CS_ADC_CAL1
          8. 8.5.4.5.8  CS_ADC_CAL2
          9. 8.5.4.5.9  ADC_CTRL1
          10. 8.5.4.5.10 ADC_CTRL2
          11. 8.5.4.5.11 ADC_CTRL3
        6. 8.5.4.6  ADC Measurement Results
          1. 8.5.4.6.1  VCELL16_HI/LO
          2. 8.5.4.6.2  VCELL15_HI/LO
          3. 8.5.4.6.3  VCELL14_HI/LO
          4. 8.5.4.6.4  VCELL13_HI/LO
          5. 8.5.4.6.5  VCELL12_HI/LO
          6. 8.5.4.6.6  VCELL11_HI/LO
          7. 8.5.4.6.7  VCELL10_HI/LO
          8. 8.5.4.6.8  VCELL9_HI/LO
          9. 8.5.4.6.9  VCELL8_HI/LO
          10. 8.5.4.6.10 VCELL7_HI/LO
          11. 8.5.4.6.11 VCELL6_HI/LO
          12. 8.5.4.6.12 VCELL5_HI/LO
          13. 8.5.4.6.13 VCELL4_HI/LO
          14. 8.5.4.6.14 VCELL3_HI/LO
          15. 8.5.4.6.15 VCELL2_HI/LO
          16. 8.5.4.6.16 VCELL1_HI/LO
          17. 8.5.4.6.17 MAIN_CURRENT_HI/LO
          18. 8.5.4.6.18 CURRENT_HI/MID/LO
          19. 8.5.4.6.19 TSREF_HI/LO
          20. 8.5.4.6.20 GPIO1_HI/LO
          21. 8.5.4.6.21 GPIO2_HI/LO
          22. 8.5.4.6.22 GPIO3_HI/LO
          23. 8.5.4.6.23 GPIO4_HI/LO
          24. 8.5.4.6.24 GPIO5_HI/LO
          25. 8.5.4.6.25 GPIO6_HI/LO
          26. 8.5.4.6.26 GPIO7_HI/LO
          27. 8.5.4.6.27 GPIO8_HI/LO
          28. 8.5.4.6.28 DIETEMP1_HI/LO
          29. 8.5.4.6.29 DIETEMP2_HI/LO
          30. 8.5.4.6.30 AUX_CELL_HI/LO
          31. 8.5.4.6.31 AUX_GPIO_HI/LO
          32. 8.5.4.6.32 AUX_BAT_HI/LO
          33. 8.5.4.6.33 AUX_REFL_HI/LO
          34. 8.5.4.6.34 AUX_VBG2_HI/LO
          35. 8.5.4.6.35 AUX_AVAO_REF_HI/LO
          36. 8.5.4.6.36 AUX_AVDD_REF_HI/LO
          37. 8.5.4.6.37 AUX_OV_DAC_HI/LO
          38. 8.5.4.6.38 AUX_UV_DAC_HI/LO
          39. 8.5.4.6.39 AUX_OT_OTCB_DAC_HI/LO
          40. 8.5.4.6.40 AUX_UT_DAC_HI/LO
          41. 8.5.4.6.41 AUX_VCBDONE_DAC_HI/LO
          42. 8.5.4.6.42 AUX_VCM_HI/LO
          43. 8.5.4.6.43 REFOVDAC_HI/LO
          44. 8.5.4.6.44 DIAG_MAIN_HI/LO
          45. 8.5.4.6.45 DIAG_AUX_HI/LO
        7. 8.5.4.7  Balancing Configuration, Control and Status
          1. 8.5.4.7.1 CB_CELL16_CTRL through CB_CELL1_CTRL
          2. 8.5.4.7.2 VCB_DONE_THRESH
          3. 8.5.4.7.3 OTCB_THRESH
          4. 8.5.4.7.4 BAL_CTRL1
          5. 8.5.4.7.5 BAL_CTRL2
          6. 8.5.4.7.6 BAL_CTRL3
          7. 8.5.4.7.7 CB_COMPLETE1
          8. 8.5.4.7.8 CB_COMPLETE2
          9. 8.5.4.7.9 BAL_TIME
        8. 8.5.4.8  Protector Configuration and Control
          1. 8.5.4.8.1 OV_THRESH
          2. 8.5.4.8.2 UV_THRESH
          3. 8.5.4.8.3 UV_DISABLE1
          4. 8.5.4.8.4 UV_DISABLE2
          5. 8.5.4.8.5 OTUT_THRESH
          6. 8.5.4.8.6 OVUV_CTRL
          7. 8.5.4.8.7 OTUT_CTRL
        9. 8.5.4.9  GPIO Configuration
          1. 8.5.4.9.1 GPIO_CONF1
          2. 8.5.4.9.2 GPIO_CONF2
          3. 8.5.4.9.3 GPIO_CONF3
          4. 8.5.4.9.4 GPIO_CONF4
        10. 8.5.4.10 SPI Master
          1. 8.5.4.10.1 SPI_CONF
          2. 8.5.4.10.2 SPI_EXE
          3. 8.5.4.10.3 SPI_TX3, SPI_TX2, and SPI_TX1
          4. 8.5.4.10.4 SPI_RX3, SPI_RX2, and SPI_RX1
        11. 8.5.4.11 Diagnostic Control
          1. 8.5.4.11.1  DIAG_OTP_CTRL
          2. 8.5.4.11.2  DIAG_COMM_CTRL
          3. 8.5.4.11.3  DIAG_PWR_CTRL
          4. 8.5.4.11.4  DIAG_CBFET_CTRL1
          5. 8.5.4.11.5  DIAG_CBFET_CTRL2
          6. 8.5.4.11.6  DIAG_COMP_CTRL1
          7. 8.5.4.11.7  DIAG_COMP_CTRL2
          8. 8.5.4.11.8  DIAG_COMP_CTRL3
          9. 8.5.4.11.9  DIAG_COMP_CTRL4
          10. 8.5.4.11.10 DIAG_PROT_CTRL
        12. 8.5.4.12 Fault Configuration and Reset
          1. 8.5.4.12.1 FAULT_MSK1
          2. 8.5.4.12.2 FAULT_MSK2
          3. 8.5.4.12.3 FAULT_RST1
          4. 8.5.4.12.4 FAULT_RST2
        13. 8.5.4.13 Fault Status
          1. 8.5.4.13.1  FAULT_SUMMARY
          2. 8.5.4.13.2  FAULT_COMM1
          3. 8.5.4.13.3  FAULT_OTP
          4. 8.5.4.13.4  FAULT_SYS
          5. 8.5.4.13.5  FAULT_PROT1
          6. 8.5.4.13.6  FAULT_PROT2
          7. 8.5.4.13.7  FAULT_OV1
          8. 8.5.4.13.8  FAULT_OV2
          9. 8.5.4.13.9  FAULT_UV1
          10. 8.5.4.13.10 FAULT_UV2
          11. 8.5.4.13.11 FAULT_OT
          12. 8.5.4.13.12 FAULT_UT
          13. 8.5.4.13.13 FAULT_COMP_GPIO
          14. 8.5.4.13.14 FAULT_COMP_VCCB1
          15. 8.5.4.13.15 FAULT_COMP_VCCB2
          16. 8.5.4.13.16 FAULT_COMP_VCOW1
          17. 8.5.4.13.17 FAULT_COMP_VCOW2
          18. 8.5.4.13.18 FAULT_COMP_CBOW1
          19. 8.5.4.13.19 FAULT_COMP_CBOW2
          20. 8.5.4.13.20 FAULT_COMP_CBFET1
          21. 8.5.4.13.21 FAULT_COMP_CBFET2
          22. 8.5.4.13.22 FAULT_COMP_MISC
          23. 8.5.4.13.23 FAULT_PWR1
          24. 8.5.4.13.24 FAULT_PWR2
          25. 8.5.4.13.25 FAULT_PWR3
        14. 8.5.4.14 Debug Control and Status
          1. 8.5.4.14.1 DEBUG_UART_RC
          2. 8.5.4.14.2 DEBUG_UART_RR_TR
          3. 8.5.4.14.3 DEBUG_UART_DISCARD
          4. 8.5.4.14.4 DEBUG_UART_VALID_HI/LO
          5. 8.5.4.14.5 DEBUG_OTP_SEC_BLK
          6. 8.5.4.14.6 DEBUG_OTP_DED_BLK
        15. 8.5.4.15 OTP Programming Control and Status
          1. 8.5.4.15.1 OTP_PROG_UNLOCK1A through OTP_PROG_UNLOCK1D
          2. 8.5.4.15.2 OTP_PROG_UNLOCK2A through OTP_PROG_UNLOCK2D
          3. 8.5.4.15.3 OTP_PROG_CTRL
          4. 8.5.4.15.4 OTP_ECC_TEST
          5. 8.5.4.15.5 OTP_ECC_DATAIN1 through OTP_ECC_DATAIN9
          6. 8.5.4.15.6 OTP_ECC_DATAOUT1 through OTP_ECC_DATAOUT9
          7. 8.5.4.15.7 OTP_PROG_STAT
          8. 8.5.4.15.8 OTP_CUST1_STAT
          9. 8.5.4.15.9 OTP_CUST2_STAT
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Application Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Cell Sensing and Balancing Inputs
          2. 9.2.1.2.2 Synchronize Voltage and Current Measurements
          3. 9.2.1.2.3 BAT and External NPN
          4. 9.2.1.2.4 Power Supplies, Reference Input
          5. 9.2.1.2.5 GPIO For Thermistor Inputs
          6. 9.2.1.2.6 Internal Balancing Current
          7. 9.2.1.2.7 UART, NFAULT
          8. 9.2.1.2.8 Current Sense Input
        3. 9.2.1.3 Application Curve
  11. 10Power Supply Recommendations
  12. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Ground Planes
      2. 11.1.2 Bypass Capacitors for Power Supplies and Reference
      3. 11.1.3 Cell Voltage Sensing
    2. 11.2 Layout Example
  13. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 サード・パーティ製品に関する免責事項
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 Trademarks
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 用語集
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.5.2 Read/Write Register Summary

Register NameAddr HexRW TypeReset ValueData
Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0
OTP_PROG_UNLOCK1A through OTP_PROG_UNLOCK1D300RW0x00CODE[7:0]
301RW0x00CODE[7:0]
302RW0x00CODE[7:0]
303RW0x00CODE[7:0]
DIR0_ADDR306RW0x00RSVDADDRESS[5:0]
DIR1_ADDR307RW0x00RSVDADDRESS[5:0]
COMM_CTRL308RW0x00RSVDRSVDRSVD
CONTROL1309RW0x00DIR_SELSEND_ SHUT DOWNSEND_ WAKESEND_ SLPTO ACTGOTO_ SHUT DOWNGOTO_ SLEEPSOFT_ RESETRSVD
CONTROL230ARW0x00RSVDRSVDTSREF _EN
OTP_PROG_CTRL30BRW0x00RSVDPAGE SELPROG _GO
ADC_CTRL130DRW0x00RSVD CS_DR[1:0]LPF_SR_ENLPF_ VCELL_ ENCS_MAIN _GO CS_MAIN_MODE[1:0]
ADC_CTRL230ERW0x00RSVDAUX_CELL_ALIGNAUX_CELL_SEL[4:0]
ADC_CTRL330FRW0x00RSVDAUX_GPIO_SEL[3:0]AUX_GOAUX_MODE[1:0]
REG_INT_RSVD310RW0x00INTERNAL USE. DO NOT WRITE TO THIS ADDRESS
CB_CELL16_CTRL through CB_CELL1_CTRL318RW0x00RSVDTIME[4:0]
319RW0x00RSVDTIME[4:0]
31ARW0x00RSVDTIME[4:0]
31BRW0x00RSVDTIME[4:0]
31CRW0x00RSVDTIME[4:0]
31DRW0x00RSVDTIME[4:0]
31ERW0x00RSVDTIME[4:0]
31FRW0x00RSVDTIME[4:0]
320RW0x00RSVDTIME[4:0]
321RW0x00RSVDTIME[4:0]
322RW0x00RSVDTIME[4:0]
323RW0x00RSVDTIME[4:0]
324RW0x00RSVDTIME[4:0]
325RW0x00RSVDTIME[4:0]
326RW0x00RSVDTIME[4:0]
327RW0x00RSVDTIME[4:0]
VCB_DONE_THRESH32ARW0x00RSVDCB_THR[5:0]
OTCB_THRESH32BRW0x0FRSVDCOOLOFF[2:0]OTCB_THR[3:0]
OVUV_CTRL32CRW0x00VCB DONE _THR _LOCKOVUV_LOCK[3:0]OVUV _GOOVUV_MODE[1:0]
OTUT_CTRL32DRW0x00RSVDOTCB_ THR_ LOCKOTUT_LOCK[2:0]OTUT _GOOTUT_MODE[1:0]
BAL_CTRL132ERW0x00RSVDDUTY[2:0]
BAL_CTRL232FRW0x00RSVDCB_ PAUSEFLTSTOP _ENOTCB_ ENBAL_ACT[1:0]BAL_GOAUTO_ BAL
BAL_CTRL3330RW0x00RSVDBAL_TIME_SEL[3:0]BAL_TIME_GO
FAULT_RST1331RW0x00RST_ PROTRST_UTRST_OTRST_UVRST_OVRST_ COMPRST_SYSRST_ PWR
FAULT_RST2332RW0x00RSVDRST_OTP _CRCRST_OTP _DATAREG_INT_RSVDREG_INT_RSVDREG_INT_RSVDREG_INT_RSVDRST_ COMM1
DIAG_OTP_CTRL335RW0x00RSVDFLIP_ FACT_ CRCMARGIN_MODE[2:0]MARGIN _GO
DIAG_COMM_CTRL336RW0x00RSVDSPI_ LOOP BACKFLIP_TR _CRC
DIAG_PWR_CTRL337RW0x00RSVDBIST_ NO_RSTPWR_ BIST_GO
DIAG_CBFET_CTRL1338RW0x00CBFET16CBFET15CBFET14CBFET13CBFET12CBFET11CBFET10CBFET9
DIAG_CBFET_CTRL2339RW0x00CBFET8CBFET7CBFET6CBFET5CBFET4CBFET3CBFET2CBFET1
DIAG_COMP_CTRL133ARW0x00VCCB_THR[4:0] REG_INT_RSVD
DIAG_COMP_CTRL233BRW0x00RSVDGPIO_THR[2:0]OW_THR[3:0]
DIAG_COMP_CTRL333CRW0x00RSVDCBFET_CTRL_GOOW_SNK[1:0]COMP_ADC_SEL[2:0]COMP_ ADC_GO
DIAG_COMP_CTRL433DRW0x00RSVDCOMP_ FAULT _INJLPF_ FAULT _INJ
DIAG_PROT_CTRL33ERW0x00RSVDPROT_ BIST_ NO_RST
OTP_ECC_DATAIN1 through OTP_ECC_DATAIN9343RW0x00DATA[7:0]
344RW0x00DATA[7:0]
345RW0x00DATA[7:0]
346RW0x00DATA[7:0]
347RW0x00DATA[7:0]
348RW0x00DATA[7:0]
349RW0x00DATA[7:0]
34ARW0x00DATA[7:0]
34BRW0x00DATA[7:0]
OTP_ECC_TEST34CRW0x00RSVDDED_ SECMANUAL _AUTOENC_ DECENABLE
SPI_CONF34DRW0x00RSVDCPOLCPHANUMBIT[4:0]
SPI_TX3, SPI_TX2, and SPI_TX134ERW0x00DATA[7:0]
34FRW0x00DATA[7:0]
350RW0x00DATA[7:0]
SPI_EXE351RW0x02RSVDSS_CTRLSPI_GO
OTP_PROG_UNLOCK2A through OTP_PROG_UNLOCK2D352RW0x00CODE[7:0]
353RW0x00CODE[7:0]
354RW0x00CODE[7:0]
355RW0x00CODE[7:0]
REG_INT_RSVD700RW0x00INTERNAL USE. DO NOT WRITE TO THIS ADDRESS
REG_INT_RSVD701RW0x00INTERNAL USE. DO NOT WRITE TO THIS ADDRESS
REG_INT_RSVD702RW0x00INTERNAL USE. DO NOT WRITE TO THIS ADDRESS