JAJSMY2B September   2021  – March 2022 CC2651R3

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 説明
  4. 4 機能ブロック図
  5. 5 Revision History
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
    1. 7.1 Pin Diagram – RGZ Package (Top View)
    2. 7.2 Signal Descriptions – RGZ Package
    3. 7.3 Pin Diagram – RKP Package (Top View)
    4. 7.4 Signal Descriptions – RKP Package
    5. 7.5 Connections for Unused Pins and Modules
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Power Supply and Modules
    5. 8.5  Power Consumption - Power Modes
    6. 8.6  Power Consumption - Radio Modes
    7. 8.7  Nonvolatile (Flash) Memory Characteristics
    8. 8.8  Thermal Resistance Characteristics
    9. 8.9  RF Frequency Bands
    10. 8.10 Bluetooth Low Energy - Receive (RX)
    11. 8.11 Bluetooth Low Energy - Transmit (TX)
    12. 8.12 Zigbee - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - RX
    13. 8.13 Zigbee - IEEE 802.15.4-2006 2.4 GHz (OQPSK DSSS1:8, 250 kbps) - TX
    14. 8.14 Timing and Switching Characteristics
      1. 8.14.1 Reset Timing
      2. 8.14.2 Wakeup Timing
      3. 8.14.3 Clock Specifications
        1. 8.14.3.1 48 MHz Crystal Oscillator (XOSC_HF)
        2. 8.14.3.2 48 MHz RC Oscillator (RCOSC_HF)
        3. 8.14.3.3 32.768 kHz Crystal Oscillator (XOSC_LF)
        4. 8.14.3.4 32 kHz RC Oscillator (RCOSC_LF)
      4. 8.14.4 Synchronous Serial Interface (SSI) Characteristics
        1. 8.14.4.1 Synchronous Serial Interface (SSI) Characteristics
        2.       37
      5. 8.14.5 UART
        1. 8.14.5.1 UART Characteristics
    15. 8.15 Peripheral Characteristics
      1. 8.15.1 ADC
        1. 8.15.1.1 Analog-to-Digital Converter (ADC) Characteristics
      2. 8.15.2 DAC
        1. 8.15.2.1 Digital-to-Analog Converter (DAC) Characteristics
      3. 8.15.3 Temperature and Battery Monitor
        1. 8.15.3.1 Temperature Sensor
        2. 8.15.3.2 Battery Monitor
      4. 8.15.4 Comparator
        1. 8.15.4.1 Continuous Time Comparator
      5. 8.15.5 GPIO
        1. 8.15.5.1 GPIO DC Characteristics
    16. 8.16 Typical Characteristics
      1. 8.16.1 MCU Current
      2. 8.16.2 RX Current
      3. 8.16.3 TX Current
      4. 8.16.4 RX Performance
      5. 8.16.5 TX Performance
      6. 8.16.6 ADC Performance
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  System CPU
    3. 9.3  Radio (RF Core)
      1. 9.3.1 Bluetooth 5.2 Low Energy
      2. 9.3.2 802.15.4 (Zigbee and 6LoWPAN)
    4. 9.4  Memory
    5. 9.5  Cryptography
    6. 9.6  Timers
    7. 9.7  Serial Peripherals and I/O
    8. 9.8  Battery and Temperature Monitor
    9. 9.9  µDMA
    10. 9.10 Debug
    11. 9.11 Power Management
    12. 9.12 Clock Systems
    13. 9.13 Network Processor
  10. 10Application, Implementation, and Layout
    1. 10.1 Reference Designs
    2. 10.2 Junction Temperature Calculation
  11. 11Device and Documentation Support
    1. 11.1 Device Nomenclature
    2. 11.2 Tools and Software
      1. 11.2.1 SimpleLink™ Microcontroller Platform
    3. 11.3 Documentation Support
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.7 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and VDDS = 3.0 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Flash sector size 8 KB
Supported flash erase cycles before failure, full bank(1)(5) 30 k Cycles
Supported flash erase cycles before failure, single sector(2) 60 k Cycles
Maximum number of write operations per row before sector erase(3) 83 Write Operations
Flash retention 105 °C 11.4 Years
Flash sector erase current Average delta current 9.7 mA
Flash sector erase time(4) Zero cycles 10 ms
30k cycles 4000 ms
Flash write current Average delta current, 4 bytes at a time 5.3 mA
Flash write time(4) 4 bytes at a time 21.6 µs
(1) A full bank erase is counted as a single erase cycle on each sector.
(2) Up to 4 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k cycles
(3) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum number of write operations per row is reached.
(4) This number is dependent on Flash aging and increases over time and erase cycles
(5) Aborting flash during erase or program modes is not a safe operation.