JAJSNG3D June   2013  – February 2024 CDCE913-Q1 , CDCEL913-Q1

PRODUCTION DATA  

  1.   1
  2. 特長
  3. アプリケーション
  4. 概要
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Control Terminal Configuration
      2. 8.3.2 Default Device Configuration
      3. 8.3.3 I2C Serial Interface
      4. 8.3.4 Data Protocol
    4. 8.4 Device Functional Modes
      1. 8.4.1 SDA and SCL Hardware Interface
    5. 8.5 Programming
  10. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Spread-Spectrum Clock (SSC)
        2. 9.2.2.2 PLL Frequency Planning
        3. 9.2.2.3 Crystal Oscillator Start-Up
        4. 9.2.2.4 Frequency Adjustment With Crystal Oscillator Pulling
        5. 9.2.2.5 Unused Inputs and Outputs
        6. 9.2.2.6 Switching Between XO and VCXO Mode
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Register Maps
    1. 10.1 I2C Configuration Registers
  12. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 ドキュメントの更新通知を受け取る方法
    3. 11.3 サポート・リソース
    4. 11.4 商標
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Overview

The CDCE913-Q1 and CDCEL913-Q1 devices are modular PLL-based, low-cost, high-performance, programmable clock synthesizers, multipliers, and dividers. They generate up to three output clocks from a single input frequency. Each output can be programmed in-system for any clock frequency up to 230 MHz, using the integrated configurable PLL.

The CDCE913-Q1 and CDCEL913-Q1 devices have separate output supply pins, VDDOUT, with output of 1.8 V for the CDCEL913-Q1 device and 2.5 V to 3.3 V for the CDCE913-Q1 device. Additionally, each device requires a 1.8-V supply applied to the VDD pin for the device to operate.

The input accepts an external crystal or LVCMOS clock signal. If an external crystal is used, an on-chip load capacitor is adequate for most applications. The value of the load capacitor is programmable from 0 pF to 20 pF. Additionally, a selectable on-chip VCXO allows synchronization of the output frequency to an external control signal, that is, the PWM signal.

The deep M / N divider ratio allows the generation of zero-ppm audio-video, networking (WLAN, Bluetooth, Ethernet, GPS) or interface (USB, IEEE1394, memory stick) clocks from, for example, a 27-MHz reference input frequency.

The PLL supports spread-spectrum clocking (SSC). SSC can be center-spread or down-spread clocking, which is a common technique to reduce electromagnetic interference (EMI).

Based on the PLL frequency and the divider settings, the internal loop filter components are automatically adjusted to achieve high stability and optimized jitter transfer characteristics.

The device supports nonvolatile EEPROM programming for easy customization of the device to the application. The device is preset to a factory default configuration (see Default Device Configuration) that can be reprogrammed to a different application configuration before PCB assembly, or reprogrammed by in-system programming. All device settings are programmable through the SDA-SCL bus, a 2-wire serial interface.

Three programmable control inputs, S0, S1, and S2, can be used to select different frequencies, change SSC setting for lowering EMI, or control other features such as outputs disabled to low, outputs in Hi-Z state, power down, PLL bypass, and so forth).

The CDCE913-Q1 device operates in a temperature range of –40°C to +125°C, and the CDCEL913-Q1 device operates in a temperature range of –40°C to 85°C.