SLPS384D March   2013  – April 2015 CSD87588N

PRODUCTION DATA.  

  1. 1Features
  2. 2Applications
  3. 3Description
  4. 4Revision History
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 Recommended Operating Conditions
    3. 5.3 Thermal Information
    4. 5.4 Power Block Performance
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Power Block Device Characteristics
    7. 5.7 Typical Power Block MOSFET Characteristics
  6. 6Application and Implementation
    1. 6.1 Application Information
      1. 6.1.1 Power Loss Curves
      2. 6.1.2 Safe Operating Curves (SOA)
      3. 6.1.3 Normalized Curves
      4. 6.1.4 Calculating Power Loss and SOA
        1. 6.1.4.1 Design Example
        2. 6.1.4.2 Calculating Power Loss
        3. 6.1.4.3 Calculating SOA Adjustments
  7. 7Layout
    1. 7.1 Layout Guidelines
      1. 7.1.1 Electrical Performance
      2. 7.1.2 Thermal Performance
    2. 7.2 Layout Example
  8. 8Device and Documentation Support
    1. 8.1 Trademarks
    2. 8.2 Electrostatic Discharge Caution
    3. 8.3 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 CSD87588N Package Dimensions
    2. 9.2 Land Pattern Recommendation
    3. 9.3 Stencil Recommendation (100 µm)
    4. 9.4 Stencil Recommendation (125 µm)
    5. 9.5 Pin Drawing
    6. 9.6 CSD87588N Embossed Carrier Tape Dimensions

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発注情報

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted) (1)
MIN MAX UNIT
Voltage VIN to PGND –0.8 30 V
VSW to PGND 30
VSW to PGND (10 ns) 32
TG to VSW –20 20
BG to PGND –20 20
IDM Pulsed Current Rating(2) 50 A
PD Power Dissipation(3) 6 W
EAS Avalanche Energy Sync FET, ID = 45, L = 0.1 mH 101 mJ
Control FET, ID = 26, L = 0.1 mH 34
TJ Operating Junction –55 150 °C
Tstg Storage Temperature Range –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Pulse Duration ≤50 µs, duty cycle ≤0.01
(3) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu

5.2 Recommended Operating Conditions

TA = 25°C (unless otherwise noted)
MIN MAX UNIT
VGS Gate Drive Voltage 4.5 16 V
VIN Input Supply Voltage 24 V
ƒSW Switching Frequency CBST = 0.1 μF (min) 200 1500 kHz
Operating Current No Airflow 25 A
With Airflow (200 LFM) 30 A
With Airflow + Heat Sink 35 A
TJ Operating Temperature 125 °C

5.3 Thermal Information

TA = 25°C (unless otherwise stated)
THERMAL METRIC MIN TYP MAX UNIT
RθJA Junction-to-ambient thermal resistance (Min Cu) (1) 170 °C/W
Junction-to-ambient thermal resistance (Max Cu) (2)(1) 70
RθJC Junction-to-case thermal resistance (Top of package) (1) 3.7
Junction-to-case thermal resistance (PGND Pin) (1) 1.25
(1) RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches
(3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board design.
(2) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu.

5.4 Power Block Performance

TA = 25°C (unless otherwise noted)
PARAMETER CONDITIONS MIN TYP MAX UNIT
PLOSS Power Loss(1) VIN = 12 V, VGS = 5 V
VOUT = 1.3 V, IOUT = 15 A
ƒSW = 500 kHz
LOUT = 0.29 µH, TJ = 25ºC 		2.1 W
IQVIN VIN Quiescent Current TG to TGR = 0 V
BG to PGND = 0 V 		10 µA
(1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5 V driver IC.

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated)
PARAMETER TEST CONDITIONS Q1 FET Q2 FET UNIT
MIN TYP MAX MIN TYP MAX
STATIC CHARACTERISTICS
BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA 30 30 V
IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 1 μA
IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 100 100 nA
VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA 1.1 1.9 1.1 1.9 V
RDS(on) Drain-to-Source On Resistance VGS = 4.5 V, IDS = 15 A 10.4 12.5 3.5 4.2 mΩ
VGS = 10 V, IDS = 15 A 8 9.6 2.9 3.5
gƒs Transconductance VDS = 10 V, IDS = 15 A 43 93 S
DYNAMIC CHARACTERISTICS
CISS Input Capacitance (1) VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz		 566 736 2310 3000 pF
COSS Output Capacitance (1) 341 444 682 887 pF
CRSS Reverse Transfer Capacitance (1) 10.3 13.4 62 80.4 pF
RG Series Gate Resistance (1) 1.2 2.4 1.1 2.2 Ω
Qg Gate Charge Total (4.5 V) (1) VDS = 15 V,
IDS = 15 A		 3.2 4.1 13.7 17.9 nC
Qgd Gate Charge - Gate-to-Drain 0.7 4.3 nC
Qgs Gate Charge - Gate-to-Source 1.4 4.3 nC
Qg(th) Gate Charge at Vth 0.8 2.8 nC
QOSS Output Charge VDD = 12 V, VGS = 0 V 7 18.6 nC
td(on) Turn On Delay Time VDS = 15 V, VGS = 4.5 V,
IDS = 15 A, RG = 2 Ω		 7.3 12.1 ns
tr Rise Time 31.6 36.7 ns
td(off) Turn Off Delay Time 10.2 20.1 ns
tƒ Fall Time 5.0 6.3 ns
DIODE CHARACTERISTICS
VSD Diode Forward Voltage IDS = 15 A, VGS = 0 V 0.85 0.78 V
Qrr Reverse Recovery Charge Vdd = 15 V, IF = 15 A,
di/dt = 300 A/μs		 12.5 26.7 nC
trr Reverse Recovery Time 16 23 ns
(1) Specified by design
CSD87588N Thermal_Max.gif
 Max RθJA = 70°C/W when mounted on 1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick) Cu.
CSD87588N Thermal_Min.gif
 Max RθJA = 170°C/W when mounted on minimum pad area of
2 oz. (0.071 mm thick) Cu.

5.6 Typical Power Block Device Characteristics

TJ = 125°C, unless stated otherwise.The Typical Power Block System Characteristic curves Figure 3 and Figure 4 are based on measurements made on a PCB design with dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (H) and 6 copper layers of 1 oz. copper thickness. See Application and Implementation for detailed explanation.
CSD87588N graph_01_SLPS384_F.png
Figure 1. Power Loss vs Output Current
CSD87588N graph_03_SLPS384_F.png
Figure 3. Safe Operating Area – PCB Horizontal Mount
CSD87588N graph_02_SLPS384_F.png
Figure 2. Normalized Power Loss vs Temperature
CSD87588N graph_04_SLPS384_F.png
Figure 4. Typical Safe Operating Area
CSD87588N graph_05_SLPS384_F2.png
Figure 5. Normalized Power Loss vs Switching Frequency
CSD87588N graph_07_SLPS384_F.png
Figure 7. Normalized Power Loss vs Output Voltage
CSD87588N graph_06_SLPS384_F.png
Figure 6. Normalized Power Loss vs Input Voltage
CSD87588N graph_08_SLPS384_F.png
Figure 8. Normalized Power Loss vs Output Inductance

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise.
CSD87588N graph_09_SLPS384_F.png
Figure 9. Control MOSFET Saturation
CSD87588N graph_11_SLPS384_F2.png
Figure 11. Control MOSFET Transfer
CSD87588N graph_13_SLPS384_F2.png
Figure 13. Control MOSFET Gate Charge
CSD87588N graph_15_SLPS384D.png
Figure 15. Control MOSFET Capacitance
CSD87588N graph_17_SLPS384_F.png
Figure 17. Control MOSFET VGS(th)
CSD87588N graph_19_SLPS384_F.png
Figure 19. Control MOSFET RDS(on) vs VGS
CSD87588N graph_21_SLPS384_F.png
Figure 21. Control MOSFET Normalized RDS(on)
CSD87588N graph_23_SLPS384_F.png
Figure 23. Control MOSFET Body Diode
CSD87588N graph_25_SLPS384_F.png
Figure 25. Control MOSFET Unclamped Inductive Switching
CSD87588N graph_10_SLPS384_F.png
Figure 10. Sync MOSFET Saturation
CSD87588N graph_12_SLPS384_F.png
Figure 12. Sync MOSFET Transfer
CSD87588N graph_14_SLPS384_F.png
Figure 14. Sync MOSFET Gate Charge
CSD87588N graph_16_SLPS384D.png
Figure 16. Sync MOSFET Capacitance
CSD87588N graph_18_SLPS384_F.png
Figure 18. Sync MOSFET VGS(th)
CSD87588N graph_20_SLPS384_F.png
Figure 20. Sync MOSFET RDS(on) vs VGS
CSD87588N graph_22_SLPS384_F.png
Figure 22. Sync MOSFET Normalized RDS(on)
CSD87588N graph_24_SLPS384_F.png
Figure 24. Sync MOSFET Body Diode
CSD87588N graph_26_SLPS384_F.png
Figure 26. Sync MOSFET Unclamped Inductive Switching