SLAS808E February   2012  – September 2015 DAC34SH84


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - DC Specifications
    6. 6.6  Electrical Characteristics - Digital Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements - Digital Specifications
    9. 6.9  Switching Characteristics - AC Specifications
    10. 6.10 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interface
      2. 7.3.2  Data Interface
      3. 7.3.3  Data Format
      4. 7.3.4  Input FIFO
      5. 7.3.5  FIFO Modes of Operation
        1. Dual-Sync-Sources Mode
        2. Single-Sync-Source Mode
        3. Bypass Mode
      6. 7.3.6  Clocking Modes
        1. PLL Bypass Mode
        2. PLL Mode
      7. 7.3.7  FIR Filters
      8. 7.3.8  Complex Signal Mixer
        1. Full Complex Mixer
        2. Coarse Complex Mixer
        3. Mixer Gain
        4. Real Channel Upconversion
      9. 7.3.9  Quadrature Modulation Correction (QMC)
        1. Gain and Phase Correction
        2. Offset Correction
      10. 7.3.10 Temperature Sensor
      11. 7.3.11 Data Pattern Checker
      12. 7.3.12 Parity Check Test
        1. 32-Bit Parity
        2. Dual 16-Bit Parity
      13. 7.3.13 DAC34SH84 Alarm Monitoring
      14. 7.3.14 LVPECL Inputs
      15. 7.3.15 LVDS Inputs
      16. 7.3.16 CMOS Digital Inputs
      17. 7.3.17 Reference Operation
      18. 7.3.18 DAC Transfer Function
      19. 7.3.19 Analog Current Outputs
    4. 7.4 Device Functional Modes
      1. 7.4.1 Multi-Device Synchronization
        1. Multi-Device Synchronization: PLL Bypassed with Dual Sync Sources Mode
        2. Multi-Device Synchronization: PLL Enabled with Dual Sync Sources Mode
        3. Multi-Device Operation: Single Sync Source Mode
    5. 7.5 Programming
      1. 7.5.1 Power-Up Sequence
      2. 7.5.2 Example Start-Up Routine
        1. Device Configuration
        2. PLL Configuration
        3. NCO Configuration
        4. Example Start-Up Sequence
    6. 7.6 Register Map
      1. 7.6.1 Register Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 IF Based LTE Transmitter
        1. Design Requirements
        2. Detailed Design Procedure
          1. Data Input Rate
          2. Interpolation
          3. LO Feedthrough and Sideband Correction
        3. Application Curves
      2. 8.2.2 Direct Upconversion (Zero IF) LTE Transmitter
        1. Design Requirements
        2. Detailed Design Procedure
          1. Data Input Rate
          2. Interpolation
          3. LO Feedthrough and Sideband Correction
        3. Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Assembly
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
      2. 11.1.2 Device Nomenclature
        1. Definition of Specifications
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Community Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information



10 Layout

10.1 Layout Guidelines

The design of the PCB is critical to achieve the full performance of the DAC34SH84 device. Defining the PCB stackup should be the first step in the board design. Experience has shown that at least six layers are required to adequately route all required signals to and from the device. Each signal routing layer must have an adjacent solid ground plane to control signal return paths to have minimal loop areas and to achieve controlled impedances for microstrip and stripline routing. Power planes must also have adjacent solid ground planes to control supply return paths. Minimizing the space between supply and ground planes improves performance by increasing the distributed decoupling.

Although the DAC34SH84 device consists of both analog and digital circuitry, TI highly recommends solid ground planes that encompass the device and its input and output signal paths. TI does not recommend split ground planes that divide the analog and digital portions of the device. Split ground planes may improve performance if a nearby, noisy, digital device is corrupting the ground reference of the analog signal path. When split ground planes are employed, one must carefully control the supply return paths and keep the paths on top of their respective ground reference planes.

Quality analog output signals and input conversion clock signal path layout is required for full dynamic performance. Symmetry of the differential signal paths and discrete components in the path is mandatory, and symmetrical shunt-oriented components should have a common grounding via. The high frequency requirements of the analog output and clock signal paths necessitate using differential routing with controlled impedances and minimizing signal path stubs (including vias) when possible.

Coupling onto or between the clock and output signals paths should be avoided using any isolation techniques available including distance isolation, orientation planning to prevent field coupling of components like inductors and transformers, and providing well coupled reference planes. Via stitching around the clock signal path and the input analog signal path provides a quiet ground reference for the critical signal paths and reduces noise coupling onto these paths. Sensitive signal traces must not cross other signal traces or power routing on adjacent PCB layers, rather a ground plane must separate the traces. If necessary, the traces should cross at 90° angles to minimize crosstalk.

The substrate (dielectric) material requirements of the PCB are largely influenced by the speed and length of the high speed serial lanes. Affordable and common FR4 varieties are adequate in most cases.

Coupling of ambient signals into the signal path is reduced by providing quiet, close reference planes and by maintaining signal path symmetry to ensure the coupled noise is common-mode. Faraday caging may be used in very noise environment and high dynamic range applications to isolate the signal path.

The following layout guidelines correspond to the layout shown in Figure 97.

  1. DAC output termination resistors should be placed as close to the output pins as possible to provide a DC path to ground and set the source impedance matching.
  2. For DAC on-chip PLL clocking mode, if the external loop filter is not used, leave the loop filter pin floating without any board routing nearby. Signals coupling to this node may cause clock mixing spurs in the DAC output.
  3. Route the high speed LVDS lanes as impedance-controlled, tightly-coupled, differential traces.
  4. Maintain a solid ground plane under the LVDS lanes without any ground plane splits.
  5. Simulation of the LVDS channel with DAC34SH84 IBIS model is recommended to verify good eye opening of the data patterns.
  6. Keep the OSTR signal routing away from the DACCLK routing to reduce coupling.
  7. Keep routing for RBIAS short, for instance a resistor can be placed on the board directly connecting the RBIAS pin to the ground layer.

The following layout guidelines correspond to the layouts shown in Figure 98 and Figure 99.

  1. Noise power supplies should be routed away from clean supplies. Use two power plane layers, preferably with a ground layer in between.
  2. As shown in Figure 98 and Figure 99, both layers three and four are designated for power supply planes. The DAC analog powers are all in the same layer to avoid coupling with each other, and the planes are copied from layer three to layer four for double the copper coverage area.
  3. Decoupling capacitors should be placed as close to the supply pins as possible. For instance, a capacitor can be placed on the bottom of the board directly connecting the supply pin to a ground layer.

10.1.1 Assembly

Information regarding the package and assembly of the ZAY package version of the DAC34SH84 can be found at the end of the data sheet and also on the following application note: SPRAA99

10.2 Layout Examples

DAC34SH84 top_later_las751.gif Figure 97. Top Layer of DAC34SH84 Layout Showing High Speed Signals such as LVDS Bus, DACCLK, OSTR, and DAC Outputs. Layout Example from TSW3085EVM Rev D
DAC34SH84 3rd_layer_las751.gif Figure 98. Third Layer of DAC34SH84 Layout Showing Power Layers. Layout Example from DAC34SH84EVM Rev H
DAC34SH84 6th_layer_las751.gif Figure 99. Sixth Layer of DAC34SH84 Layout Showing Power Layers. Layout Example from DAC34SH84EVM Rev H