JAJSCY4D December 2016 – December 2023 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93
PRODUCTION DATA
デバイスごとのパッケージ図は、PDF版データシートをご参照ください。
15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | x |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 |
R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
15:8 | MATCH_DATA | R/W | 0x1C | The character to match for buffer release. Normally it is a /R/=/K28.0/-0x1C but with these bits the user can program the value. |
7 | MATCH_SPECIFIC | R/W | 1 | Match a specific character to start the JESD buffering when asserted; otherwise the first non-K will start the buffering. |
6 | MATCH_CTRL | R/W | 1 | When asserted the match character is a CONTROL character instead of a DATA character. |
5 | NO_LANE_SYNC | R/W | 0 | Assert if the TX side does not support lane initialization. This way the RX won’t flag errors in the configuration portion of the ILA. |
4:2 | Not Used | R/W | 000 | Not Used |
1 | Reserved | R/W | 0 | Reserved |
0 | JESD_COMMAALIGN_ENA | R/W | 1 | When asserted the JESD block SERDES comma align signal will be added with the SERDES ALIGN bit(0) to control when to shut off comma alignment. When this bit is deasserted; then the programmed bit(spi_config62(11)) is the only control. |