JAJSCY4D December 2016 – December 2023 DAC38RF80 , DAC38RF83 , DAC38RF84 , DAC38RF85 , DAC38RF90 , DAC38RF93
PRODUCTION DATA
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MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
Digital Input Timing Specifications | ||||||
Timing: SYSREF+/- | ||||||
ts(SYSREF) | Setup time, SYSREF+/- valid to rising edge of DACCLK+/- | SYSREF Capture assist disabled | 50 | ps | ||
th(SYSREF) | Hold time, SYSREF+/- valid after rising edge of DACCLK+/- | SYSREF Capture assist disabled | 50 | ps | ||
Timing: SeriaL Port | ||||||
ts(/SDEN) | Setup time, SDEN to rising edge of SCLK | 20 | ns | |||
ts(SDIO) | Setup time, SDIO valid to rising edge of SCLK | 10 | ns | |||
th(SDIO) | Hold time, SDIO valid after rising edge of SCLK | 5 | ns | |||
t(SCLK) | Period of SCLK | temperature sensor read | 1 | µs | ||
All other registers | 100 | ns | ||||
td(Data) | Data output delay after falling edge of SCLK | 25 | ns | |||
tRESET | Minimum RESET pulse width | 25 | ns | |||
Analog Output | ||||||
ts(DAC) | Output settling time to 0.1% | 1 | ns | |||
tr | Output rise time 10% to 90% | 50 | ps | |||
tf | Output fall time 90% to 10% | 50 | ps | |||
Latency | ||||||
RX SerDes AnalogDelay | 250 | ps | ||||
DAC wake-up time | IOUT current settling to 1% of IOUTFS from deep sleep | 90 | µs | |||
DAC sleep time | IOUT current settling to less than 1% of IOUTFS in deep sleep | 90 | µs |