• The full-scale IDAC output range is 350 mA. The nominal IDAC output for this application is 120 mA. The IDAC code required to set the IDAC output to 120 mA is calculated by Equation 8.

• The IDAC uses the internal reference. Enable the internal reference in the COMMON-CONFIG register before enabling the IDAC output.

• The power dissipation of the IDAC channel is a function of the PV_DD supply voltage, the current output, and the voltage of the IDAC pin (V_IDAC). The headroom voltage (V_HEADROOM) is calculated as the difference between PV_DD and V_IDAC. Minimize V_HEADROOM to reduce the power dissipation of the device while also meeting the minimum V_HEADROOM requirement. The IDAC output cannot source the full-scale current output if V_HEADROOM is lower than the specified voltage. Figure 8-2 shows the output current directions and the key voltages that impact power dissipation. The IDAC output contributes to power dissipation proportionally to the output current multiplied by the V_HEADROOM voltage.

Figure 8-2 IDAC Power Dissipation

• The VOUT1 channel of the DAC53xAxW can be configured as a programmable comparator. In the DAC-1-GAIN-CMP-CONFIG register:
  • Enable the channel for comparator mode,
  • Enable the comparator output,
  • Disable Hi-Z input mode, and
  • Set the reference for the comparator.
  This application example uses the 3.3-V V_DD as the reference with a 1× gain. The programmable threshold (V_THRESH) is set in the DAC-1-DATA register for the respective channel. Equation 9 calculates the DAC code for a 1-V threshold.

• Configure the function of the GPIO/SDO pin in the GPIO-CONFIG register. The GPI-EN bit enables the GPIO/SDO pin as an input. The GPI-CH-SEL field selects which channels are controlled by the GPI. The GPI-CONFIG field selects the GPI function. Table 6-8 defines the functions for the GPI-CONFIG field. This application uses the GPIO/SDO pin to set the IDAC output to margin high or margin low. Set both the DAC-2-MARGIN-HIGH and DAC-2-MARGIN-LOW registers to zero-scale to clear the outputs to zero when the GPIO/SDO pin is toggled. A falling edge on the GPIO/SDO pin clears the IDAC to zero-scale. After the GPIO/SDO pin returns high, set the IDAC output to the desired output code using the DAC-2-DATA register.
• In this application circuit, the comparator output is connected to the GPIO input to clear the IDAC output zero-scale. When V_IDAC is less than V_THRESH, the comparator output is high and the IDAC output remains at the programmed code in the DAC-2-DATA register. When V_IDAC is greater than V_THRESH, the comparator output is set low and the IDAC output is cleared to zero-scale. This is the default configuration of the comparator. To reverse the comparator output polarity, set the CMP-1-INV-EN bit in the DAC-1-GAIN-CMP-CONFIG register to 1.

The pseudocode for a camera auto-focus control application is as follows:

//SYNTAX: WRITE <REGISTER NAME (Hex code)>, <MSB DATA>, <LSB DATA>
//Write DAC code for nominal IDAC output
//The 10-bit hex code for 120 mA is 0x160. With 16-bit left alignment, this becomes 0x5800
WRITE DAC-2-DATA(0x19), 0x58, 0x00
//Set VOUT1 gain setting to 1x VDD (3.3 V), enable comparator mode, enable comparator output, disable hi-z input
WRITE DAC-1-GAIN-CMP-CONFIG(0x15), 0x04, 0x0D
//For a 3.3-V output range, the 10-bit hex code for 1 V is 0x136. With 16-bit left alignment, this becomes 0x4D80
WRITE DAC-1-DATA(0x1C), 0x4D, 0x80
//Power-up output on IDAC and VDAC channels, enables internal reference 
WRITE COMMON-CONFIG(0x1F), 0x13, 0xDF 
//Configure GPI for margin high, margin low trigger for IDAC channel
WRITE GPIO-CONFIG(0x24), 0x00, 0x35 
//Save settings to NVM 
WRITE COMMON-TRIGGER(0x20), 0x00, 0x02