SGLS387H July   2007  – August 2016 DAC5675A-SP

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 DC Electrical Characteristics (Unchanged After 100 kRad)
    6. 7.6 AC Electrical Characteristics (Unchanged After 100 kRad)
    7. 7.7 Digital Specifications (Unchanged After 100 kRad)
    8. 7.8 Electrical Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Digital Inputs
      2. 8.3.2 Clock Input
      3. 8.3.3 Supply Inputs
      4. 8.3.4 DAC Transfer Function
      5. 8.3.5 Reference Operation
      6. 8.3.6 Analog Current Outputs
    4. 8.4 Device Functional Modes
      1. 8.4.1 Sleep Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Definitions of Specifications and Terminology
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • HFG|52
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

HFG Package
52-Pin CQFP
(Top View)
DAC5675A-SP hfga_52_gls387.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND 13, 20, 26, 39, 44, 49, 50, 52 I Analog negative supply voltage (ground). Pin 13 is internally connected to the heat slug and lid (lid is also grounded internally).
AVDD 21, 45, 48, 51 I Analog positive supply voltage
BIASJ 42 O Full-scale output current bias
CLK 23 I External clock input
CLKC 22 I Complementary external clock
D[13:0]A 1, 3, 5, 7, 9, 11, 14, 24, 27, 29, 31, 33, 35, 37 I LVDS positive input, data bits 13–0.
D13A is the most significant data bit (MSB).
D0A is the least significant data bit (LSB).
D[13:0]B 2, 4, 6, 8, 10, 12, 15, 25, 28, 30, 32, 34, 36, 38 I LVDS negative input, data bits 13–0.
D13B is the most significant data bit (MSB).
D0B is the least significant data bit (LSB).
DGND 17, 19 I Digital negative supply voltage (ground)
DVDD 16, 18 I Digital positive supply voltage
EXTIO 43 I/O Internal reference output or external reference input. Requires a 0.1-μF decoupling capacitor to AGND when used as reference output.
IOUT1 46 O DAC current output. Full-scale when all input bits are set '0'. Connect the reference side of the DAC load resistors to AVDD.
IOUT2 47 O DAC complementary current output. Full-scale when all input bits are '1'. Connect the reference side of the DAC load resistors to AVDD.
NC 41 Not connected in chip. Can be high or low.
SLEEP 40 I Asynchronous hardware power-down input. Active high. Internal pulldown.